Datasheet

Data Sheet AD9547
Rev. E | Page 9 of 104
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Rise/Fall Time
1
(20% to 80%)
10 pF load
3.3 V Supply
Strong Drive Strength Setting
0.5
2
ns
Weak Drive Strength Setting 8 14.5 ns
1.8 V Supply
1.5
2.5
ns
Duty Cycle
40
60
%
10 pF load
Output Voltage High (V
OH
) Output driver static; strong drive
strength setting
AVDD3 = 3.3 V, I
OH
= 10 mA 2.6 V
AVDD3 = 3.3 V, I
OH
= 1 mA 2.9 V
AVDD3 = 1.8 V, I
OH
= 1 mA 1.5 V
Output Voltage Low (V
OL
)
Output driver static; strong drive
strength setting
AVDD3 = 3.3 V, I
OL
= 10 mA 0.3 V
AVDD3 = 3.3 V, I
OL
= 1 mA 0.1 V
AVDD3 = 1.8 V, I
OL
= 1 mA
0.1
V
OUTPUT TIMING SKEW 10 pF load
Between LVPECL Outputs 14 125 ps Rising edge only; any divide value
Between LVDS Outputs 13 138 ps Rising edge only; any divide value
Between CMOS (3.3 V) Outputs
Strong Drive Strength Setting
23
240
ps
Weak Drive Strength Setting
24
ps
Between CMOS (1.8 V) Outputs
40
ps
Weak drive option not supported at 1.8 V
Between LVPECL Outputs and LVDS
Outputs
14
140
ps
Between LVPECL Outputs and
CMOS Outputs
19
ps
ZERO-DELAY TIMING SKEW
±5
ns
Output relative to active input reference;
output distribution synchronization to
active reference feature enabled;
assumes manual phase offset
compensation of deterministic latency
1
The listed values are for the slower edge (rising or falling).
DAC OUTPUT CHARACTERISTICS (DACOUTP, DACOUTN)
Table 12.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
FREQUENCY RANGE 62.5 450 MHz
OUTPUT OFFSET VOLTAGE
15
mV
This is the single-ended voltage at either
DAC output pin (no external load) when
the internal DAC code is such that no
current is delivered to that pin
VOLTAGE COMPLIANCE RANGE VSS − 0.5 0.5 VSS + 0.5 V
OUTPUT RESISTANCE
50
Ω
Single-ended; each pin has an internal
50 Ω termination to VSS
OUTPUT CAPACITANCE
5
pF
FULL-SCALE OUTPUT CURRENT 20 mA Programmable (8 mA to 31 mA; see the
DAC Output section)
GAIN ERROR
−12
+12
% FS