Datasheet

Data Sheet AD9547
Rev. E | Page 75 of 104
CLOCK DISTRIBUTION OUTPUT CONFIGURATION (REGISTER 0x0400 TO REGISTER 0x0417)
Table 67. Distribution Settings
1
Address
Bit
Bit Name
Description
0x0400 [7:6] Unused Unused.
5
External distribution resistor
Output current control for the clock distribution outputs.
0 (default) = internal current setting resistor.
1 = external current setting resistor.
4 Receiver mode Clock distribution receiver mode.
0 (default) = normal operation.
1 = high frequency mode (super-Nyquist).
[3:2] Unused Write a 1 to these bits.
1
OUT1 power-down
Power down clock distribution output OUT1.
0 (default) = normal operation.
1 = power down.
0 OUT0 power-down Power down clock distribution output OUT0.
0 (default) = normal operation.
1 = power-down.
1
When Bits [1:0] = 11, the clock distribution output enters a deep sleep mode.
Table 68. Distribution Enable
Address
Bit
Bit Name
Description
0x0401 [7:2] Unused Unused.
1
OUT1 enable
Enable the OUT1 driver.
0 (default) = disable.
1 = enable.
0 OUT0 enable Enable the OUT0 driver.
0 (default) = disable.
1 = enable.
Table 69. Distribution Synchronization
Address
Bit
Bit Name
Description
0x0402
[7:6]
Unused
Unused.
[5:4]
Sync source
Select the sync source for the clock distribution output channels.
00 (default) = direct.
01 = active reference.
10 = DPLL feedback edge.
11 = reserved.
[3:2]
Unused
Unused.
1
OUT1 sync mask
Mask the synchronous reset to the OUT1 divider.
0 (default) = unmasked.
1 = masked.
0 OUT0 sync mask Mask the synchronous reset to the OUT0 divider.
0 (default) = unmasked.
1 = masked.
Table 70. Automatic Synchronization
Address
Bit
Bit Name
Description
0x0403 [7:2] Unused Unused.
[1:0]
Automatic sync mode
Autosync mode.
00 (default) = disabled.
01 = sync on DPLL frequency lock.
10 = sync on DPLL phase lock.
11 = reserved.