Datasheet

AD9547 Data Sheet
Rev. E | Page 74 of 104
Table 63. Incremental Closed-Loop Phase Lock Offset Step Size
1
Address
Bit
Bit Name
Description
0x0314 [7:0] Incremental phase lock offset
step size (expressed in ps/step)
Incremental phase lock offset step size, Bits[7:0].
0x0315
[7:0]
Incremental phase lock offset step size, Bits[15:8].
1
The default incremental closed loop phase lock offset step size value is 0x03E8 = 1000 (1 ns).
Table 64. Phase Slew Rate Limit
1
Address Bit Bit Name Description
0x0316
[7:0]
Phase slew rate limit
(expressed in ns/sec)
Phase slew rate limit, Bits[7:0].
0x0317 [7:0] Phase slew rate limit, Bits[15:8].
1
The default phase slew rate limit is 0 (or disabled).
Table 65. History Accumulation Timer
1
Address
Bit
Bit Name
Description
0x0318 [7:0] History accumulation timer
(expressed in ms)
History accumulation timer, Bits[7:0].
0x0319
[7:0]
History accumulation timer, Bits[15:8].
0x031A [7:0] History accumulation timer, Bits[23:16].
1
Do not program a timer value of 0. The history accumulation timer default value is 0x007530 = 30,000 (30 sec).
Table 66. History Mode
Address
Bit
Bit Name
Description
0x031B [7:5] Unused Unused.
4
Single sample fallback
Controls the holdover history. If tuning word history is not available for the
reference that was active just prior to holdover, then
0 (default) = use the free-running frequency tuning word register value.
1 = use the last tuning word from the DPLL.
3
Persistent history
Controls the holdover history initialization. When switching to a new reference
0 (default) = clear the tuning word history.
1 = retain the previous tuning word history.
[2:0] Incremental average History mode value from 0 to 7 (default = 0).