Datasheet

Data Sheet AD9547
Rev. E | Page 71 of 104
Register 0x0209 to Register 0x0210—IRQ Mask
The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (Address 0x0D02 to Address 0x0D09).
When set to Logic 1, the IRQ mask bits enable the corresponding IRQ monitor bits to indicate an IRQ event. The default for all IRQ mask
bits is Logic 0, which prevents the IRQ monitor from detecting any internal interrupts.
Table 51. IRQ Mask for SYSCLK
Address
Bit
Bit Name
Description
0x0209
[7:6]
Unused
Unused.
5
SYSCLK unlocked
Enables IRQ for indicating a SYSCLK PLL state transition from locked to unlocked.
4 SYSCLK locked Enables IRQ for indicating a SYSCLK PLL state transition from unlocked to locked.
[3:2]
Unused
Unused.
1 SYSCLK cal complete Enables IRQ for indicating that SYSCLK calibration is complete.
0
SYSCLK cal started
Enables IRQ for indicating that SYSCLK calibration has begun.
Table 52. IRQ Mask for Distribution Sync, Watchdog Timer, and EEPROM
Address
Bit
Bit Name
Description
0x020A [7:4] Unused Unused.
3
Distribution sync
Enables IRQ for indicating a distribution sync event.
2
Watchdog timer
Enables IRQ for indicating expiration of the watchdog timer.
1 EEPROM fault Enables IRQ for indicating a fault during an EEPROM load or save operation.
0
EEPROM complete
Enables IRQ for indicating successful completion of an EEPROM load or save operation.
Table 53. IRQ Mask for the Digital PLL
Address
Bit
Bit Name
Description
0x020B 7 Switching Enables IRQ for indicating that the DPLL is switching to a new reference.
6
Closed
Enables IRQ for indicating that the DPLL has entered closed-loop operation.
5 Free run Enables IRQ for indicating that the DPLL has entered free-run mode.
4
Holdover
Enables IRQ for indicating that the DPLL has entered holdover mode.
3
Frequency unlocked
Enables IRQ for indicating that the DPLL lost frequency lock.
2
Frequency locked
Enables IRQ for indicating that the DPLL has acquired frequency lock.
1 Phase unlocked Enables IRQ for indicating that the DPLL lost phase lock.
0
Phase locked
Enables IRQ for indicating that the DPLL has acquired phase lock.
Table 54. IRQ Mask for History Update, Frequency Limit, and Phase Slew Limit
Address
Bit
Bit Name
Description
0x020C
[7:5]
Unused
Unused.
4
History updated
Enables IRQ for indicating the occurrence of a tuning word history update.
3 Frequency unclamped Enables IRQ for indicating a state transition of the frequency limiter from clamped to
unclamped.
2 Frequency clamped Enables IRQ for indicating a state transition of the frequency limiter from unclamped to
clamped.
1 Phase slew unlimited Enables IRQ for indicating a state transition of the phase slew limiter from slew limiting to
not slew limiting.
0
Phase slew limited
Enables IRQ for indicating a state transition of the phase slew limiter from not slew
limiting to slew limiting.