Datasheet

Data Sheet AD9547
Rev. E | Page 65 of 104
Addr
Opt
1
Name
D7
D6
D5
D4
D3
D2
D1
D0
Def
0x06D4
S divider
S[15:0]
0x00
0x06D5
0x00
0x06D6 Unused S[19:16] 0x00
0x06D7
Unused
0x00
0x06D8
Fractional
feedback
divider
V[7:0]
0x00
0x06D9
U[3:0]
Unused
V[9:8]
0x00
0x06DA
Unused
U[9:4]
0x00
0x06DB
Lock
detectors
Phase lock threshold[15:0] (in ps)
0x00
0x06DC
0x00
0x06DD
Phase lock fill rate[7:0]
0x00
0x06DE
Phase lock drain rate[7:0]
0x00
0x06DF
Frequency lock threshold[23:0] (in ps)
0x00
0x06E0
0x00
0x06E1
0x00
0x06E2
Frequency lock fill rate[7:0]
0x00
0x06E3 Frequency lock drain rate[7:0] 0x00
0x06E4
to
0x06FF
Unused
Profile registers—Profile 4 through Profile 7
0x0700
to
0x07FF
Profile 4
through
Profile 7
The functionality of the Profile 4 through Profile 7 address locations (Address 0x0700 to Address 0x07FF) is identical to
that of the Profile 0 through Profile 3 address locations (Address 0x0600 to Address 0x06FF)
Operational controls
0x0A00
S
General
power-down
Reset sans
regmap
Unused
SYSCLK
power-
down
Reference
power-
down
TDC
power-
down
DAC
power-
down
Dist
power-
down
Full
power-
down
0x00
0x0A01 C Loop mode Unused User
holdover
User
free run
User selection mode[1:0] Unused
(write a 0
to this bit)
User reference
selection[1:0]
0x00
0x0A02
S
Cal/sync
Unused
Sync
distribution
Calibrate
SYSCLK
0x00
0x0A03
A, C
Reset
functions
Unused
Clear LF
Clear CCI
C le ar phase
accumulator
Reset auto
sync
Reset
TW history
Reset
all IRQs
Reset
watchdog
0x00
0x0A04
A, C
IRQ clearing
Unused
SYSCLK
unlocked
SYSCLK
locked
Unused
SYSCLK cal
complete
SYSCLK cal
started
0x00
0x0A05
A, C
Unused
Distribu-
tion sync
Watchdog
timer
EEPROM
fault
EEPROM
complete
0x00
0x0A06
A, C
Switching
Closed
Free run
Holdover
Frequency
unlocked
Frequency
locked
Phase
unlocked
Phase
locked
0x00
0x0A07
A, C
Unused
History
updated
Frequency
unclamped
Frequency
clamped
Phase slew
unlimited
Phase slew
limited
0x00
0x0A08
A, C
Ref AA
new profile
Ref AA
validated
Ref AA fault
cleared
Ref AA fault
Ref A
new profile
Ref A
validated
Ref A
fault cleared
Ref A
fault
0x00
0x0A09
A, C
Ref BB
new profile
Ref BB
validated
Ref BB
fault cleared
Ref BB
fault
Ref B
new profile
Ref B
validated
Ref B
fault cleared
Ref B
fault
0x00
0x0A0A
A, C
Unused
0x00
0x0A0B
A, C
Unused
0x00
0x0A0C A, C Incremental
phase offset
Unused Reset
phase of fset
Decrement
phase offset
Increment
phase offset
0x00
0x0A0D A, C Reference
profile selec-
tion state
machine
startup
Unused Detect BB Detect B Detect AA Detect A 0x00
0x0A0E A, C Force
validation
timeout
Unused Force
Timeout BB
Force
Timeout B
Force
Timeout AA
Force
Timeout A
0x00
0x0A0F
C
Reference
monitor
override
Unused
Ref Mon
Override
BB
Ref Mon
Override B
Ref Mon
Override AA
Ref Mon
Override A
0x00
0x0A10 C Reference
monitor
bypass
Unused Ref Mon
Bypass BB
Ref Mon
Bypass B
Ref Mon
Bypass AA
Ref Mon
Bypass A
0x00