Datasheet

AD9547 Data Sheet
Rev. E | Page 6 of 104
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Low Frequency Path
Input Frequency Range
3.5
100
MHz
Minimum Input Slew Rate
50
V/µs
Minimum limit imposed for jitter performance
Common-Mode Voltage 1.2 V Internally generated
Differential Input Voltage Sensitivity
100
mV p-p
This is the minimum voltage required across the pins to
ensure switching between logic states; the
instantaneous voltage on either pin must not exceed
the supply rails; ac ground the unused input to
accommodate single-ended operation
Input Capacitance 3 pF Single-ended, each pin
Input Resistance 4 kΩ
Crystal Resonator Path
Crystal Resonator Frequency Range
10
50
MHz
Fundamental mode, AT cut
Maximum Crystal Motional
Resistance
100
Ω
See the System Clock Inputs section for recommendations
DISTRIBUTION CLOCK INPUTS (CLKINP, CLKINN)
Table 7.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT FREQUENCY RANGE 62.5 500 MHz
MINIMUM SLEW RATE
75
V/µs
Minimum limit imposed for jitter performance
COMMON-MODE VOLTAGE
700
mV
Internally generated
DIFFERENTIAL INPUT VOLTAGE SENSITIVITY 100 mV p-p Capacitive coupling required; ac ground the unused
input to accommodate single-ended operation; the
instantaneous voltage on either pin must not exceed
the supply rails
D
IFFERENTIAL INPUT POWER SENSITIVITY
−15 dBm S
ame as voltage sensitivity but specified as power into a
50 Ω load
INPUT CAPACITANCE 3 pF
INPUT RESISTANCE
5
kΩ
Each pin has a 2.5 kΩ internal dc bias resistance