Datasheet

AD9547 Data Sheet
Rev. E | Page 54 of 104
Table 34. Serial Control Port Timing
Parameter Description
t
DS
Setup time between data and the rising edge of SCLK.
t
DH
Hold time between data and the rising edge of SCLK.
t
CLK
Period of the clock.
t
S
Setup time between the
CS
falling edge and SCLK rising edge (start of the communication cycle).
t
C
Setup time between the SCLK rising edge and the
CS
rising edge (end of the communication cycle). To ensure that
SDIO/SDO do not tristate before the last data bit (D0) is read, it is recommended that a ½ SCLK cycle be used for t
c
.
t
HIGH
Minimum period that SCLK should be in a logic high state.
t
LOW
Minimum period that SCLK should be in a logic low state.
t
DV
SCLK to valid SDIO and SDO (see Figure 56).