Datasheet

Data Sheet AD9547
Rev. E | Page 5 of 104
LOGIC INPUTS (M0 TO M7, RESET)
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
I NP UT VOLTA GE
Input High Voltage (V
IH
)
2.1
V
Input Low Voltage (V
IL
)
V
INPUT CURRENT (I
INH
, I
INL
) ±80 ±200 µA
INPUT CAPACITANCE (C
IN
) 3 pF
LOGIC OUTPUTS (M0 TO M7, IRQ)
Table 5.
Parameter
Min
Typ
Unit
Test Conditions/Comments
OUTPUT VOLTAGE
Output High Voltage (V
OH
) 2.7 V I
OH
= 1 mA
Output Low Voltage (V
OL
) 0.4 V I
OL
= 1 mA
IRQ LEAKAGE CURRENT
Open-drain mode
Active Low Output Mode
µA
V
OH
= 3.3 V
Active High Output Mode
µA
V
OL
= 0 V
SYSTEM CLOCK INPUTS (SYSCLKP, SYSCLKN)
Table 6.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SYSTEM CLOCK PLL BYPASSED
Input Frequency Range 500 1000 MHz
Minimum Input Slew Rate 1000 V/µs Minimum limit imposed for jitter performance
Duty Cycle
40
60
%
Common-Mode Voltage
1.2
V
Internally generated
Differential Input Voltage Sensitivity
100
mV p-p
Minimum voltage across pins is required to ensure
switching between logic states; the instantaneous
voltage on either pin must not exceed the supply rails;
ac ground the unused input to accommodate si ngl e-
ended operation
Input Capacitance
2
pF
Single-ended, each pin
Input Resistance 2.5 kΩ
SYSTEM CLOCK PLL ENABLED
PLL Output Frequency Range
900
1000
MHz
Phase Frequency Detector (PFD) Rate
150
MHz
Frequency Multiplication Range 6 255 Assumes valid system clock and PFD rates
VCO Gain
70
MHz/V
High Frequency Path
Input Frequency Range 100.1 500 MHz
Minimum Input Slew Rate 200 V/µs Minimum limit imposed for jitter performance
Frequency Divider Range 1 8 Binary steps (M = 1, 2, 4, 8)
Common-Mode Voltage
1 V Internally generated
Differential Input Voltage Sensitivity
100
mV p-p
This is the minimum voltage required across the pins to
ensure switching between logic states; the
instantaneous voltage on either pin must not exceed
the supply rails; ac ground the unused input to
accommodate single-ended operation
Input Capacitance
3
pF
Single-ended, each pin
Input Resistance
2.5
kΩ