Datasheet
AD9547 Data Sheet
Rev. E | Page 4 of 104
SPECIFICATIONS
Minimum and maximum values apply for the full range of supply voltage and operating temperature variation. Typical values apply for
AVDD3 = DVDD3 = 3.3 V, AVDD = DVDD
= 1.8 V, T
A
= 25°C, I
DAC
= 20 mA (full scale), unless otherwise noted.
SUPPLY VOLTAGE
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DVDD3
3.135
3.30
3.465
V
Pin 7, Pin 58
DVDD 1.71 1.80 1.89 V Pin 1, Pin 6, Pin 8, Pin 10, Pin 11, Pin 53, Pin 59, Pin 64
AVDD3
3.135
3.30
3.465
V
Pin 16, Pin 33, Pin 43, Pin 49
3.3 V Supply (Typical)
3.135
3.30
3.465
V
Pin 25, Pin 31
1.8 V Supply (Alternative)
1.71
1.80
1.89
V
Pin 25, Pin 31
AVDD 1.71 1.80 1.89 V Pin 17, Pin 18, Pin 23, Pin 28, Pin 32, Pin 36, Pin 39, Pin 42, Pin 46, Pin 50
SUPPLY CURRENT
The test conditions for the maximum supply current are the same as the test conditions for the All Blocks Running section of Table 3. The
test conditions for the typical supply current are the same as the test conditions for the Typical Configuration section of Table 3.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
I
DVDD3
1.5 3 mA Pin 7, Pin 58
I
DVDD
190
215
mA
Pin 1, Pin 6, Pin 8, Pin 10, Pin 11, Pin 53, Pin 59, Pin 64
I
AVDD3
52 70 mA Pin 16, Pin 33, Pin 43, Pin 49
3.3 V Supply (Typical) 24 55 mA Pin 25, Pin 31
1.8 V Supply (Alternative) 24 55 mA Pin 25, Pin 31
I
AVDD
135
150
mA
Pin 17, Pin 18, Pin 23, Pin 28, Pin 32, Pin 36, Pin 39, Pin 42, Pin 46, Pin 50
POWER DISSIPATION
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
TYPICAL CONFIGURATION
800
1100
mW
f
SYSCLK
= 20 MHz
1
; f
S
= 1 GHz
2
; f
DDS
= 122.88 MHz
3
; one LVPECL clock
distribution output running at 122.88 MHz (all others powered
down); one input reference running at 100 MHz (all others
powered down)
ALL BLOCKS RUNNING
900
1250
mW
f
SYSCLK
= 20 MHz
1
; f
S
= 1 GHz
2
; f
DDS
= 399 MHz
3
; all clock distribution
outputs configured as LVPECL at 399 MHz; all input references
configured as differential at 100 MHz; fractional-N active (R = 10,
S = 39, U = 9, V = 10)
FULL POWER-DOWN
13
mW
Conditions = typical configuration; no external pull-up or pull-
down resistors
INCREMENTAL POWER DISSIPATION Conditions = typical configuration; table values show the change
in power due to the indicated operation
SYSCLK PLL Off
−105
mW
f
SYSCLK
= 1 GHz
1
; high frequency direct input mode
Input Reference On
Differential 7 mW
Single-Ended 13 mW
Output Distribution Driver On
LVDS 70 mW
LVPECL
75
mW
CMOS
65
mW
Single 3.3 V CMOS output with a 10 pF load
1
f
SYSCLK
is the frequency at the SYSCLKP and SYSCLKN pins.
2
f
S
is the sample rate of the output DAC.
3
f
DDS
is the output frequency of the DDS.