Datasheet

AD9547 Data Sheet
Rev. E | Page 26 of 104
THEORY OF OPERATION
TW CLAMP
AND
HISTORY
PROG.
DIGITAL
LOOP
FILTER
TDC/PFD
÷R
÷S
DIGITAL PLL CORE
HOLDOVER
LOGIC
CONTROL
LOGIC
LOW NOISE
CLOCK
MULTIPLIER
AMP
SYSCLK PORT
INPUT
REF
MONITOR
IRQ AND
STATUS
LOGIC
DIGITAL
INTERFACE
IRQ
SYSCLKN SYSCLKP
CLKINN
CLKINP
M0 TO M7
REFA
REFAA
OUT0P
PHASE
CONTROLLER
DDS/DAC
AD9547
2 OR 4
OUT0N
OUT_RSET
OUT1P
OUT1N
POST
DIV
POST
DIV
CLOCK
DISTRIBUTION
REFB
REFBB
DIFFERENTIAL
OR
SINGLE-ENDED
EXTERNAL
ANALOG
FILTER
08300-009
Figure 32. Detailed Block Diagram
OVERVIEW
The AD9547 provides clocking outputs that are directly related
in phase and frequency to the selected (active) reference but with
jitter characteristics primarily governed by the system clock. The
AD9547 supports up to four reference inputs and a wide range of
reference frequencies. The core of this product is a digital phase-
locked loop (DPLL). The DPLL has a programmable digital loop
filter that greatly reduces jitter transferred from the active
reference to the output. The AD9547 supports both manual and
automatic holdover modes. While in holdover mode, the AD9547
continues to provide an output as long as the DAC sample clock
is present. The holdover output frequency is a time average of
the output frequency history just prior to the transition to the
holdover condition.
The device offers manual and automatic reference switchover
capability if the active reference is degraded or fails completely.
A direct digital synthesizer (DDS) and integrated DAC constitute
a digitally controlled oscillator (DCO). The DCO output is
a sinusoidal signal (450 MHz maximum) at a frequency that is
determined by the active reference frequency and the programmed
values of the reference prescaler (R) and feedback divider (S).
Although not explicitly shown in Figure 32, the S divider has
both an integer and fractional component, which is similar to
a fractional-N synthesizer.
The SYSCLKx input provides the sample clock for the DAC, which
is either a directly applied high frequency source or a low frequency
source coupled with the integrated PLL-based frequency multiplier.
The low frequency option also allows for the use of a crystal
resonator connected directly across the SYSCLKx inputs.
The DAC output routes directly off chip where an external filter
removes the sampling artifacts before returning the signal on chip
at the CLKINx inputs. Once on chip, an integrated comparator
converts the filtered sinusoidal signal to a clock signal (square
wave) with very fast rise and fall times.
The clock distribution section provides two output drivers. Each
driver is programmable either as a single differential LVPECL/
LVDS output or as a dual single-ended CMOS output. Further-
more, a dedicated 30-bit programmable divider precedes each
driver. The clock distribution section operates at up to 725 MHz.
This enables use of a band-pass reconstruction filter (for example,
a SAW filter) to extract a Nyquist image from the DAC output
spectrum, thereby allowing output frequencies that exceed the
typical 450 MHz limit at the DAC output.