Datasheet

Data Sheet AD9547
Rev. E | Page 17 of 104
Pin No.
Input/
Output
Pin Type Mnemonic Description
47 I Differential
input
REFB Reference B Input. This internally biased input is typically ac-coupled and,
when configured as such, can accept any differential signal with a single-ended
swing of up to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.
48
I
Differential
input
REFBB
Complementary Reference B Input. Complementary signal to the input provided
on Pin 47. The user can configure this pin as a separate single-ended input.
51
I
NC
No Connection. This pin should be left floating.
52 O Logic IRQ Interrupt Request Line.
54, 55, 56, 57,
60, 61, 62, 63
I/O 3.3 V CMOS M0, M1, M2, M3,
M4, M5, M6, M7
Configurable I/O Pins. These pins are configured under program control.
EP
O
Exposed
pad
Exposed pad
The exposed pad must be connected to ground (VSS).