Datasheet

AD9547 Data Sheet
Rev. E | Page 12 of 104
SERIAL PORT SPECIFICATIONS—I
2
C MODE
Table 18.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SDA (AS INPUT), SCL No internal pull-up/pull-down
resistor
Input Logic 1 Voltage 0.7 × DVDD3 V
Input Logic 0 Voltage 0.3 × DVDD3 V
Input Current −10 +10 µA For V
IN
= 10% to 90% of DVDD3
Hysteresis of Schmitt Trigger Inputs
0.015 × DVDD3
V
Pulse Width of Spikes That Must Be
Suppressed by the Input Filter, t
SP
50
ns
SDA (AS OUTPUT)
Output Logic 0 Voltage
0.4
V
I
O
= 3 mA
Output Fall Time from V
IHmin
to V
ILmax
20 + 0.1 C
b
1
250 ns 10 pF ≤ C
b
≤ 400 pF
TIMING
SCL Clock Rate
400
kHz
Bus Free Time Between a Stop and Start
Condition, t
BUF
1.3
µs
Repeated Start Condition Setup Time, t
SU;S TA
0.6
µs
Repeated Hold Time Start Condition, t
HD;S TA
0.6
µs
After this period, the first clock
pulse is generated
Stop Condition Setup Time, t
SU;STO
0.6
µs
Low Period of the SCL Clock, t
LOW
1.3
µs
High Period of the SCL Clock, t
HIGH
0.6 µs
SCL/SDA Rise Time, t
R
20 + 0.1 C
b
1
300 ns
SCL/SDA Fall Time, t
F
20 + 0.1 C
b
1
300 ns
Data Setup Time, t
SU;DAT
100
ns
Data Hold Time, t
HD;DAT
100
ns
Capacitive Load for Each Bus Line, C
b
1
400
pF
1
C
b
is the capacitance (pF) of a single bus line.