Datasheet

Data Sheet AD9547
Rev. E | Page 11 of 104
SERIAL PORT SPECIFICATIONS—SPI MODE
Table 17.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CS Internal 30 kΩ pull-up resistor
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 30 µA
Input Logic 0 Current 110 µA
Input Capacitance
2
pF
SCLK Internal 30 kΩ pull-down resistor
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current
1
µA
Input Logic 0 Current
1
µA
Input Capacitance
2
pF
SDIO
As an Input
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 1 µA
Input Logic 0 Current
1
µA
Input Capacitance
2
pF
As an Output
Output Logic 1 Voltage 2.7 V 1 mA load current
Output Logic 0 Voltage 0.4 V 1 mA load current
SDO
Output Logic 1 Voltage
2.7
V
1 mA load current
Output Logic 0 Voltage 0.4 V 1 mA load current
TIMING
SCLK
Clock Rate, 1/t
CLK
40 MHz
Pulse Width High, t
HIGH
10
ns
Pulse Width Low, t
LOW
12
ns
SDIO to SCLK Setup, t
DS
3
ns
SCLK to SDIO Hold, t
DH
0 ns
SCLK to Valid SDIO and SDO, t
DV
15 ns
CS
to SCLK Setup, t
S 10 ns
CS
to SCLK Hold, t
C
0
ns
CS
Minimum Pulse Width High
6
ns