Datasheet

AD9547 Data Sheet
Rev. E | Page 10 of 104
TIME DURATION OF DIGITAL FUNCTIONS
Table 13.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
EEPROM-TO-REGISTER DOWNLOAD TIME 25 ms Using default EEPROM storage sequence
(see Register 0x0E10 to Register 0x0E3F)
REGISTER-TO-EEPROM UPLOAD TIME 200 ms Using default EEPROM storage sequence
(see Register 0x0E10 to Register 0x0E3F
MINIMUM POWER-DOWN EXIT TIME
10.5
µs
Dependent on loop filter bandwidth
MAXIMUM TIME FROM ASSERTION OF THE RESET PIN
TO THE M0 TO M7 PINS ENTERING HIGH
IMPEDANCE STATE
45 ns
DIGITAL PLL
Table 14.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PHASE FREQUENCY DETECTOR (PFD) INPUT
FREQUENCY RANGE
0.001 10 MHz Maximum f
PFD
= f
S
/100
1, 2
LOOP BANDWIDTH 0.001 1 × 10
5
Hz Programmable design parameter;
maximum f
LOOP
= f
REF
/(20R)
3
PHASE MARGIN
30
89
Degrees
Programmable design parameter
REFERENCE INPUT (R) DIVISION FACTOR
1
2
30
1, 2, …1,073,741,824
INTEGER FEEDBACK (S) DIVISION FACTOR 8 2
20
8, 9, …1,048,576
FRACTIONAL FEEDBACK DIVIDE RATIO
0
0.999
Maximum value = 1022/1023
1
f
PFD
is the frequency at the input to the phase-frequency detector.
2
f
S
is the sample rate of the output DAC.
3
f
REF
is the frequency of the active reference; R is the frequency division factor determined by the R divider.
DIGITAL PLL LOCK DETECTION
Table 15.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PHASE LOCK DETECTOR
Threshold Programming Range
0.001
65.5
ns
Threshold Resolution 1 ps
FREQUENCY LOCK DETECTOR
Threshold Programming Range
0.001
16,700
ns
Reference-to-feedback period difference
Threshold Resolution
1
ps
HOLDOVER SPECIFICATIONS
Table 16.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
FREQUENCY ACCURACY <0.01 ppb Excludes frequency drift of SYSCLK source;
excludes frequency drift of input reference
prior to entering holdover