Datasheet

ManualsBrandsANALOG DEVICES ManualsClock & Timing ICsLFCSP 64 VQ

Dual/Quad Input Network Clock

Generator/Synchronizer

Data Sheet

AD9547

Rev. E Document Feedback

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FEATURES

Supports Stratum 2 stability in holdover mode

Supports reference switchover with phase build-out

Supports hitless reference switchover

Automatic/manual holdover and reference switchover

2 pairs of reference input pins, with each pair configurable

as a single differential input or as 2 independent single-

ended inputs

Input reference frequencies from 1 kHz to 750 MHz

Reference validation and frequency monitoring (1 ppm)

Programmable input reference switchover priority

30-bit programmable input reference divider

2 pairs of clock output pins, with each pair configurable as

a single differential LVDS/LVPECL output or as 2 single-

ended CMOS outputs

Output frequencies up to 450 MHz

20-bit integer and 10-bit fractional programmable feedback

divider

Programmable digital loop filter covering loop bandwidths

from 0.001 Hz to 100 kHz

Optional low noise LC-VCO system clock multiplier

Optional crystal resonator for system clock input

On-chip EEPROM to store multiple power-up profiles

Software controlled power-down

64-lead LFCSP package

APPLICATIONS

Network synchronization

Cleanup of reference clock jitter

SONET/SDH clocks up to OC-192, including FEC

Stratum 2 holdover, jitter cleanup, and phase transient

control

Stratum 3E and Stratum 3 reference clocks

Wireless base stations, controllers

Cable infrastructure

Data communications

GENERAL DESCRIPTION

The AD9547 provides synchronization for many systems,

including synchronous optical networks (SONET/SDH). The

AD9547 generates an output clock that is synchronized to one

of two differential or four single-ended external input references.

The digital PLL allows for reduction of input time jitter or phase

noise associated with the external references. The AD9547

continuously generates a clean (low jitter), valid output clock,

even when all references fail, by means of digitally controlled

loop and holdover circuitry.

The AD9547 operates over an industrial temperature range of

−40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

REFERENCE INPUTS

AND

MONITOR MUX

STATUS AND

CONTROL PINS

SERIAL CONTROL INTERFACE

(SPI or I

EEPROM

DIGITAL

PLL

CLOCK DISTRIBUTION

SYNC

DAC

CLOCK

MULTIPLIER

STABLE

SOURCE

ANALOG

FILTER

AD9547

CHANNEL 0

DIVIDER

CHANNEL 1

DIVIDER

08300-001

Figure 1.

Summary of content (104 pages)

PAGE 1
Dual/Quad Input Network Clock Generator/Synchronizer AD9547 Data Sheet FEATURES APPLICATIONS Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Automatic/manual holdover and reference switchover 2 pairs of reference input pins, with each pair configurable as a single differential input or as 2 independent singleended inputs Input reference frequencies from 1 kHz to 750 MHz Reference validation and frequency monitoring (1
PAGE 2
AD9547 Data Sheet TABLE OF CONTENTS Features .....................................................................................1 Digital Phase-Locked Loop (DPLL) Core............................ 32 Applications...............................................................................1 Direct Digital Synthesizer (DDS)......................................... 34 General Description ..................................................................1 Tuning Word Processing.......................
PAGE 3
Data Sheet AD9547 EEPROM Storage Sequence (Register 0x0E10 to Register 0x0E3F)................................................................... 96 Thermal Performance ....................................................... 100 Applications Information...................................................... 100 Outline Dimensions.............................................................. 104 Power Supply Partitions..................................................... 100 Ordering Guide ............
PAGE 4
AD9547 Data Sheet SPECIFICATIONS Minimum and maximum values apply for the full range of supply voltage and operating temperature variation. Typical values apply for AVDD3 = DVDD3 = 3.3 V, AVDD = DVDD = 1.8 V, TA = 25°C, IDAC = 20 mA (full scale), unless otherwise noted. SUPPLY VOLTAGE Table 1. Parameter DVDD3 DVDD AVDD3 3.3 V Supply (Typical) 1.8 V Supply (Alternative) AVDD Min 3.135 1.71 3.135 3.135 1.71 1.71 Typ 3.30 1.80 3.30 3.30 1.80 1.80 Max 3.465 1.89 3.465 3.465 1.89 1.
PAGE 5
Data Sheet AD9547 LOGIC INPUTS (M0 TO M7, RESET) Table 4. Parameter INPUT VOLTAGE Input High Voltage (VIH) Input Low Voltage (VIL) INPUT CURRENT (IINH, IINL) INPUT CAPACITANCE (CIN) Min Typ Max Unit 0.8 ±200 V V µA pF Max Unit Test Conditions/Comments 0.4 V V 1 1 µA µA IOH = 1 mA IOL = 1 mA Open-drain mode VOH = 3.3 V VOL = 0 V Max Unit 1000 MHz V/µs % V mV p-p 2.1 ±80 3 Test Conditions/Comments LOGIC OUTPUTS (M0 TO M7, IRQ) Table 5.
PAGE 6
AD9547 Parameter Low Frequency Path Input Frequency Range Minimum Input Slew Rate Common-Mode Voltage Differential Input Voltage Sensitivity Input Capacitance Input Resistance Crystal Resonator Path Crystal Resonator Frequency Range Maximum Crystal Motional Resistance Data Sheet Min Typ 3.5 50 Max Unit 100 MHz V/µs V mV p-p 1.
PAGE 7
Data Sheet AD9547 REFERENCE INPUTS (REFA/REFAA, REFB/REFBB) Table 8. Parameter DIFFERENTIAL OPERATION Frequency Range Sinusoidal Input LVPECL Input LVDS Input Minimum Input Slew Rate Common-Mode Input Voltage Differential Input Voltage Sensitivity Input Resistance Input Capacitance Minimum Pulse Width High Minimum Pulse Width Low SINGLE-ENDED OPERATION Frequency Range (CMOS) Minimum Input Slew Rate Input Voltage High (VIH) 1.2 V to 1.5 V Threshold Setting 1.8 V to 2.5 V Threshold Setting 3.0 V to 3.
PAGE 8
AD9547 Data Sheet REFERENCE SWITCHOVER SPECIFICATIONS Table 10.
PAGE 9
Data Sheet Parameter Rise/Fall Time 1 (20% to 80%) 3.3 V Supply Strong Drive Strength Setting Weak Drive Strength Setting 1.8 V Supply Duty Cycle Output Voltage High (VOH) AVDD3 = 3.3 V, IOH = 10 mA AVDD3 = 3.3 V, IOH = 1 mA AVDD3 = 1.8 V, IOH = 1 mA Output Voltage Low (VOL) AD9547 Min Max Unit 0.5 8 1.5 2 14.5 2.5 60 ns ns ns % 40 2.6 2.9 1.
PAGE 10
AD9547 Data Sheet TIME DURATION OF DIGITAL FUNCTIONS Table 13. Parameter EEPROM-TO-REGISTER DOWNLOAD TIME Min Typ 25 Max Unit ms REGISTER-TO-EEPROM UPLOAD TIME 200 ms MINIMUM POWER-DOWN EXIT TIME MAXIMUM TIME FROM ASSERTION OF THE RESET PIN TO THE M0 TO M7 PINS ENTERING HIGH IMPEDANCE STATE 10.
PAGE 11
Data Sheet AD9547 SERIAL PORT SPECIFICATIONS—SPI MODE Table 17.
PAGE 12
AD9547 Data Sheet SERIAL PORT SPECIFICATIONS—I2C MODE Table 18.
PAGE 13
Data Sheet AD9547 JITTER GENERATION Table 19. Parameter CONDITIONS: fREF = 8 kHz 1, fDDS = 155.52 MHz 2, fLOOP = 100 Hz 3 Min Typ Max Unit Bandwidth: 100 Hz to 77 MHz Bandwidth: 5 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Bandwidth: 50 kHz to 80 MHz Bandwidth: 4 MHz to 80 MHz CONDITIONS: fREF = 19.44 MHz1, fDDS = 155.52 MHz2, fLOOP = 1 kHz3 0.71 0.34 0.43 0.43 0.
PAGE 14
AD9547 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 20. Parameter Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Digital I/O Supply Voltage (DVDD3) DAC Supply Voltage (AVDD3) Maximum Digital Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating 2V 2V 3.6 V 3.6 V −0.5 V to DVDD3 + 0.
PAGE 15
Data Sheet AD9547 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVDD M7 M6 M5 M4 DVDD DVDD3 M3 M2 M1 M0 DVDD IRQ NC AVDD AVDD3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9547 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 REFBB REFB AVDD REFAA REFA AVDD3 AVDD TDC_VRT TDC_VRB AVDD SYSCLKP SYSCLKN AVDD SYSCLK_LF SYSCLK_VREG AVDD3 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND (VSS).
PAGE 16
AD9547 Data Sheet Pin No.
PAGE 17
Data Sheet Pin No. 47 Input/ Output I 48 I 51 52 54, 55, 56, 57, 60, 61, 62, 63 EP I O I/O O AD9547 Pin Type Differential input Mnemonic REFB Differential input REFBB Logic 3.3 V CMOS Exposed pad NC IRQ M0, M1, M2, M3, M4, M5, M6, M7 Exposed pad Description Reference B Input. This internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with a single-ended swing of up to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.
PAGE 18
AD9547 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS fREF = input reference clock frequency, fO = clock frequency, fSYSCLK = SYSCLK input frequency, fS =internal system clock frequency, LBW = DPLL loop bandwidth, PLL off = SYSCLK PLL bypassed, PLL on = SYSCLK PLL enabled, ICP = SYSCLK PLL charge pump current, LF = SYSCLK PLL loop filter. AVDD, AVDD3, and DVDD at nominal supply voltage, fS = 1 GHz, ICP = automatic mode, LF = internal, unless otherwise noted.
PAGE 19
Data Sheet –70 –80 AD9547 –70 INTEGRATED RMS JITTER (PHASE NOISE): 5kHz TO 20MHz: 361fs (–69.0dBc) 20kHz TO 80MHz: 441fs (–67.3dBc) (EXTRAPOLATED) –80 50MHz CRYSTAL –90 –110 –120 –130 –120 –130 –140 –150 –150 10k 1k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) –160 100 ROHDE & SCHWARZ SMA100 (1GHz) 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) Figure 10. Additive Phase Noise Comparison of SYSCLK Input Options (Output Driver = LVPECL), fREF = 19.44 MHz, fO = 311.
PAGE 20
AD9547 Data Sheet 2.0 1.0 5pF LOAD 0.8 AMPLITUDE (V) AMPLITUDE (V) LVPECL 0.6 0.4 LVDS 1.5 20pF LOAD 1.0 10pF LOAD 0.2 300 400 500 600 700 FREQUENCY (MHz) 0 200 250 50 200 FREQUENCY (MHz) Figure 13. Amplitude vs. Toggle Rate, LVPECL and LVDS Figure 16. Amplitude vs. Toggle Rate, 1.8 V CMOS 4.0 4.0 3.5 3.5 10pF LOAD 5pF LOAD 3.0 AMPLITUDE (V) AMPLITUDE (V) 150 100 50 08300-062 200 08300-063 100 08300-049 0 08300-061 0.5 0 2.5 20pF LOAD 2.0 1.5 3.0 10pF LOAD 2.
PAGE 21
Data Sheet AD9547 160 34 140 32 30 10pF LOAD 100 5pF LOAD 10pF LOAD 80 28 20pF LOAD 26 60 24 40 22 20 10 0 50 150 100 200 250 300 350 FREQUENCY (MHz) 08300-060 20 15 25 20 30 35 40 FREQUENCY (MHz) Figure 19. Power Consumption vs. Frequency, 3.3 V CMOS (Strong Mode) Figure 22. Power Consumption vs. Frequency, 3.3 V CMOS (Weak Mode) 1.0 0.5 0.8 0.4 0.6 0.3 DIFFERENTIAL AMPLITUDE (V) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –1.
PAGE 22
AD9547 Data Sheet 2.0 10pF LOAD 1.5 1.0 0.5 0 –0.5 0 2 4 6 8 10 TIME (ns) 12 14 16 08300-065 AMPLITUDE (V) 20pF LOAD Figure 25. Output Waveform, 1.8 V CMOS (100 MHz) Rev.
PAGE 23
Data Sheet AD9547 INPUT/OUTPUT TERMINATION RECOMMENDATIONS 0.1µF DOWNSTREAM DEVICE 100Ω 100Ω HIGH IMPEDANCE INPUT 0.1µF AD9547 SELF-BIASED SYSCLKx INPUT 08300-006 08300-003 0.1µF (OPTIONAL) AD9547 3.3V LVDS OUTPUT 0.1µF Figure 26. AC-Coupled LVDS or LVPECL Output Driver Figure 29. SYSCLKx Input AD9547 100Ω DOWNSTREAM DEVICE 100Ω 3.3V LVPECLCOMPATIBLE OUTPUT AD9547 SELF-BIASED CLKINx INPUT 08300-007 08300-004 0.1µF (OPTIONAL) 0.1µF Figure 27.
PAGE 24
AD9547 Data Sheet GETTING STARTED POWER-ON RESET The AD9547 monitors the voltage on the power supplies at powerup. When DVDD3 is greater than 2.35 V ± 0.1 V and DVDD (Pin 1, Pin 6, Pin 8, Pin 53, Pin 59, and Pin 64) is greater than 1.4 V ± 0.05 V, the device generates a 75 ns reset pulse. The power-up reset pulse is internal and independent of the RESET pin. This internal power-up reset sequence eliminates the need for the user to provide external power supply sequencing.
PAGE 25
Data Sheet AD9547 The clock distribution parameters reside in the 0x0400 register address space. They include the following: • • • • • • Output power-down control Output enable (disabled by default) Output synchronization Output mode control Output divider functionality Program the reference inputs. Reference power-down Reference logic family Reference profile assignment control Phase build-out control 13. Generate the output clock. 11. Program the reference profiles.
PAGE 26
AD9547 Data Sheet THEORY OF OPERATION AD9547 OUT_RSET DIFFERENTIAL OR SINGLE-ENDED REFA POST DIV OUT0P OUT0N POST DIV OUT1P OUT1N REFAA REFB REFBB DIGITAL PLL CORE ÷S CLKINP TDC/PFD 2 OR 4 ÷R PROG.
PAGE 27
Data Sheet AD9547 REFERENCE CLOCK INPUTS Two pairs of pins provide access to the reference clock receivers. Each pair is configurable either as a single differential receiver or as two independent single-ended receivers. To accommodate input signals with slow rising and falling edges, both the differential and single-ended input receivers employ hysteresis. Hysteresis also ensures that a disconnected or floating input does not cause the receiver to oscillate spontaneously.
PAGE 28
AD9547 Data Sheet REGISTER CONTROL BITS REFERENCE VALIDATION LOGIC (4 COPIES, 1 PER REFERENCE INPUT) D Q VALID FORCE VALIDATION TIMEOUT VALIDATION TIMER REF MONITOR BYPASS REF MONITOR OVERRIDE R 1 EN R TIMEOUT FAULTED 08300-010 0 REFERENCE MONITOR REF FAULT Figure 33.
PAGE 29
Data Sheet AD9547 The four nibbles form a one-to-one correspondence with the four reference inputs: one nibble for REF A, the next for REF AA, and so on. For a reference configured as a differential input, however, the device ignores the nibble associated with the two-letter input. For example, if the B reference is differential, only the REF B nibble matters (the device ignores the REF BB nibble).
PAGE 30
AD9547 Data Sheet REFERENCE SWITCHOVER Automatic Priority-Based Reference Switchover An attractive feature of the AD9547 is its versatile reference switchover capability. The flexibility of the reference switchover functionality resides in a sophisticated prioritization algorithm coupled with register-based controls. This scheme provides the user with maximum control over the state machine that handles reference switchover.
PAGE 31
Data Sheet AD9547 A ACTIVE A VALID PRIORITY TABLE INPUT PRIORITY PROMOTED 0 A 0 AA 1 0 B 2 1 BB 3 2 A FAULTED AA ACTIVE AA VALID COMMON WITHOUT PROMOTION WITH PROMOTION A VALID AA FAULTED B ACTIVE AA VALID 08300-011 ALL VALID INITIAL STATE Figure 34. Example of Priority Promotion PROFILE SELECTION VALIDATION LOGIC PRIORITY SELECTION LOOP CONTROLLER … … MONITORS ÷R TDC 08300-012 … REF A/REF AA REF B/REF BB Figure 35.
PAGE 32
AD9547 Data Sheet an increase in the phase slew rate limit value or a decrease in the system clock frequency tends to reduce the error. Therefore, the accuracy is best for the largest phase slew rate limit value and the lowest system clock frequency. For example, assuming the use of a 1 GHz system clock, a phase slew rate limit value of 315 ns/sec (or more) ensures an error of <10%, whereas a phase slew rate limit value above ~3100 ns/sec ensures an error of <1%.
PAGE 33
Data Sheet AD9547 α In addition, the user can adjust the closed-loop phase offset (positive or negative) in incremental fashion. To do so, program the desired step size in the incremental phase lock offset step size bits (Address 0x0314 and Address 0x0315). This is an unsigned number that represents units of picoseconds (ps). The programmed step size is added to the current closed-loop phase offset each time the user writes a Logic 1 to the increment phase offset bit (Register 0x0A0C, Bit 0).
PAGE 34
AD9547 Data Sheet phase error sample but, rather, its magnitude relative to the phase threshold value that determines whether to fill or drain. If more filling is taking place than draining, the water level in the tub eventually rises above the high water mark (+1024), which causes the phase lock detector to indicate lock. If more draining is taking place than filling, the water level in the tub eventually falls below the low water mark (−1024), which causes the phase lock detector to indicate unlock.
PAGE 35
Data Sheet AD9547 DDS Phase Offset The relative phase of the sinusoid generated by the DDS is numerically controlled by adding a phase offset word to the output of the DDS accumulator. This is accomplished via the open loop phase offset register (Address 0x030D to Address 0x030E), which is a programmable 16-bit value (Δphase).
PAGE 36
AD9547 Data Sheet Note that history accumulation timer = 0 should not be programmed because it may cause improper device operation. The control logic performs a calculation of the average tuning word during the TAVG interval and stores the result in the holdover history register (Address 0x0D14 to Address 0x0D19). Computation of the average for each TAVG interval is independent of the previous interval (that is, the average is a memoryless average as opposed to a true moving average).
PAGE 37
Data Sheet AD9547 Recovery from Holdover When in holdover, if a valid reference becomes available, the device exits holdover operation. The loop state machine restores the DPLL to closed-loop operation, locks to the selected reference, and sequences the recovery of all the loop parameters based on the profile settings for the active reference. Note that if the user holdover bit (Register 0x0A01, Bit 6) is set, the device does not automatically exit holdover when a valid reference is available.
PAGE 38
AD9547 Data Sheet LF SYSCLKN 37 SYSCLK_VREG SYSCLK_LF 34 35 2× LOCK DETECT ÷M PFD AND CHARGE PUMP XTAL VCO CALIBRATION LOOP FILTER SYSCLKP 38 ÷N SYSTEM CLOCK 08300-020 HF Figure 44. System Clock Block Diagram The LF path permits the user to provide an LVPECL, LVDS, CMOS, or sinusoidal low frequency clock for multiplication by the integrated SYSCLK PLL. The LF path handles input frequencies from 3.5 MHz up to 100 MHz.
PAGE 39
Data Sheet AD9547 Bits[5:3]). The charge pump current varies from 125 μA to 1 mA in 125 μA steps. The default setting is 500 μA. SYSCLK PLL Loop Filter The AD9547 has an internal second-order loop filter that establishes the loop dynamics for input signals between 12.5 MHz and 100 MHz. By default, the device uses the internal loop filter. However, an external loop filter option is available by setting the external loop filter enable bit (Register 0x0100, Bit 7).
PAGE 40
AD9547 Data Sheet ratio of 1), the output duty cycle is the same as the input duty cycle. Odd output divide ratios (excluding 1) exhibit automatic duty cycle correction given by CLKINP CLKINN SYNC CONTROL SYNC SOURCE ENABLE RESET Output Duty Cycle  4 ENABLEn/MODEn 4 4 Q0 where: N (which must be an odd number) is the divide ratio. X is the normalized fraction of the high portion of the input period (that is, 0 < X < 1).
PAGE 41
Data Sheet AD9547 Table 24. Output Channel Logic Family and Pin Functionality Mode Bits [2:0] 000 001 010 011 100 101 110 111 Logic Family and Pin Functionality CMOS (both pins) CMOS (positive pin), tristate (negative pin) Tristate (positive pin), CMOS (negative pin) Tristate (both pins) LVDS LVPECL Unused Unused Regardless of the selected logic family, each is capable of dc operation.
PAGE 42
AD9547 Data Sheet active input reference. The detection of the rising edge synchronizes the distribution output. When sync source = 10, the rising edge of the primary synchronization signal triggers the circuitry that detects a rollover of the DDS accumulator (after processing by the DPLL feedback divider). This corresponds to the zero crossing of the output of the phase-toamplitude converter in the DDS (less the open-loop phase offset stored in Register 0x030D and Register 0x030E).
PAGE 43
Data Sheet AD9547 The deterministic delay, expressed as tLATENCY in the following equation, is a function of the frequency division factor (Qn) of the channel divider associated with the zero-delay channel.
PAGE 44
AD9547 Data Sheet STATUS AND CONTROL MULTIFUNCTION PINS (M0 TO M7) The AD9547 has eight digital CMOS I/O pins (M0 to M7) that are configurable for a variety of uses. The function of these pins is programmable via the register map. Each pin can control or monitor an assortment of internal functions, based on the contents of Register 0x0200 to Register 0x0207. To monitor an internal function with a multifunction pin, write a Logic 1 to the MSB of the register associated with the desired multifunction pin.
PAGE 45
Data Sheet AD9547 At power-up, the multifunction pins can be used to force the device into certain configurations as defined in the Initial M0 to M7 Pin Programming section. This functionality, however, is valid only during power-up or following a reset, after which the pins can be reconfigured via the serial programming port or via the EEPROM. IRQ PIN The AD9547 has a dedicated interrupt request (IRQ) pin.
PAGE 46
AD9547 Data Sheet   EEPROM EEPROM Overview The AD9547 contains an integrated 2048-byte electrically erasable programmable read-only memory (EEPROM). The AD9547 can be configured to perform a download at power-up via the multifunction pins (M3 to M7), but uploads and downloads can also be done on demand via the EEPROM control registers (Address 0x0E00 to Address 0x0E03). The EEPROM provides the ability to upload and download configuration settings to and from the register map.
PAGE 47
Data Sheet AD9547 Table 28. EEPROM Controller Instruction Set Instruction Value (Hex) 0x00 to 0x7F Instruction Type Data Bytes Required 3 0x80 I/O update 1 0xA0 Calibrate 1 0xA1 Distribution sync 1 0xB0 to 0xCF Condition 1 0xFE Pause 1 0xFF End 1 Description A data instruction tells the controller to transfer data to or from the device settings part of the register map. A data instruction requires two additional bytes that, together, indicate a starting address in the register map.
PAGE 48
AD9547 Data Sheet Note that conditional processing is applicable only when downloading (see the EEPROM Conditional Processing section).
PAGE 49
Data Sheet AD9547 If the condition is not tagged, the controller skips instructions until it encounters a condition instruction that decodes as a tagged condition. Note that the condition tag board allows for multiple conditions to be tagged at any given moment. This conditional processing mechanism enables the user to have one download instruction sequence with many possible outcomes, depending on the value of the condition and the order in which the controller encounters the condition instructions.
PAGE 50
AD9547 Data Sheet SERIAL CONTROL PORT SERIAL CONTROL ARBITER 13-BIT ADDRESS SPACE SPI EEPROM MULTIFUNCTION PIN CONTROL LOGIC READ-ONLY REGION I2C EEPROM CONTROLLER 400kHz READ/WRITE REGION ANALOG BLOCKS AND DIGITAL CORE M7 M6 M5 M4 M3 M2 M1 M0 08300-026 SCLK/SCL CS/SDA SDIO SDO POWER-ON RESET Figure 50.
PAGE 51
Data Sheet AD9547 SPI Mode Operation Write The SPI port supports both 3-wire (bidirectional) and 4-wire (unidirectional) hardware configurations and both MSB-first and LSB-first data formats. Both the hardware configuration and data format features are programmable. By default, the AD9547 uses the bidirectional MSB-first mode. The bidirectional mode is the default mode so that the user can still write to the device to switch to unidirectional mode, if it is wired for unidirectional operation.
PAGE 52
AD9547 Data Sheet SPI Instruction Word (16 Bits) When Register 0x0000, Bit 6 = 1 (LSB first), the instruction and data bytes must be written from LSB to MSB. Multibyte data transfers in LSB-first format start with an instruction byte that includes the register address of the least significant payload byte, followed by multiple data bytes. The serial control port internal byte address generator increments for each byte of the multibyte transfer cycle.
PAGE 53
Data Sheet AD9547 tHIGH tDH SCLK DON'T CARE SDIO DON'T CARE R/W W1 tC tCLK tLOW CS W0 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 HIGH-IMEPDANCE 08300-153 tDS tS Figure 54. Serial Control Port Read—MSB First, 16-Bit Instruction, One Byte of Data tDS tHIGH tS tDH DON'T CARE SDIO DON'T CARE DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'T CARE 08300-031 SCLK tC tCLK tLOW CS Figure 55.
PAGE 54
AD9547 Data Sheet Table 34. Serial Control Port Timing Parameter tDS tDH tCLK tS tC tHIGH tLOW tDV Description Setup time between data and the rising edge of SCLK. Hold time between data and the rising edge of SCLK. Period of the clock. Setup time between the CS falling edge and SCLK rising edge (start of the communication cycle). Setup time between the SCLK rising edge and the CS rising edge (end of the communication cycle).
PAGE 55
Data Sheet AD9547 The transfer of data appears graphically in Figure 59. One clock pulse is generated for each data bit transferred. The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can change only when the clock signal on the SCL line is low. I²C SERIAL PORT OPERATION The I2C interface has the advantage of requiring only two control pins and is a de facto standard throughout the I2C industry.
PAGE 56
AD9547 Data Sheet bytes immediately after the slave address byte are the internal memory (control registers) address bytes with the high address byte first. This addressing scheme gives a memory address up to 216 − 1 = 65,535. The data bytes after these two memory address bytes are register data written into or read from the control registers. In read mode, the data bytes after the slave address byte are register data written into or read from the control registers.
PAGE 57
Data Sheet AD9547 I²C Serial Port Timing SDA tLOW tF tR tSU;DAT tHD;STA tSP tBUF tR tF tHD;STA S tHD;DAT tHIGH tSU;STO tSU;STA Sr Figure 64. I²C Serial Port Timing Table 36.
PAGE 58
AD9547 Data Sheet I/O PROGRAMMING REGISTERS BUFFERED/ACTIVE REGISTERS There are two broad categories of registers on the AD9547: buffered and active (see Figure 65). Buffered registers are those that can be written to directly from the serial port. They do not need an I/O update to apply their contents to the internal device functions. In contrast, active registers require an I/O update to transfer data between the buffered registers and the internal device functions.
PAGE 59
Data Sheet AD9547 REGISTER MAP The register addresses and defaults are hexadecimal values. Use the default value when writing to registers or bits marked as unused. Table 37.
PAGE 60
AD9547 Data Sheet Addr DPLL 0x0300 0x0301 0x0302 0x0303 0x0304 0x0305 0x0306 0x0307 0x0308 0x0309 0x030A 0x030B 0x030C 0x030D 0x030E 0x030F 0x0310 0x0311 0x0312 0x0313 0x0314 0x0315 Opt 1 Name C C C C C C A, C C C C C C C C C C C C C C C C Free-running frequency tuning word Free-running frequency tuning word[47:0] Update TW Pull-in range lower limit Unused Pull-in range lower limit[23:0] Pull-in range upper limit Pull-in range upper limit[23:0] Open-loop phase offset Open-loop phase offset word
PAGE 61
Data Sheet Addr Opt 1 Name 0x0410 S Reserved 0x0411 S 0x0412 S 0x0413 S 0x0414 S 0x0415 S 0x0416 S 0x0417 S Reference input configuration 0x0500 S Reference power-down 0x0501 0x0502 0x0503 S S C 0x0504 C 0x0505 0x0506 0x0507 C C C Reference logic family Manual reference profile selection Phase buildout switching Profile registers—Profile 0 0x0600 Priorities 0x0601 Reference period 0x0602 0x0603 0x0604 0x0605 0x0606 0x0607 0x0608 Tolerance 0x0609 0x060A 0x060B 0x060C 0x060D 0x060E Validation timer 0x0
PAGE 62
AD9547 Data Sheet Addr Opt 1 Name 0x061E R divider 0x061F 0x0620 0x0621 0x0622 S divider 0x0623 0x0624 0x0625 0x0626 Fractional feedback 0x0627 divider 0x0628 0x0629 Lock detectors 0x062A 0x062B 0x062C 0x062D 0x062E 0x062F 0x0630 0x0631 Profile registers—Profile 1 0x0632 Priorities 0x0633 0x0634 0x0635 0x0636 0x0637 0x0638 0x0639 0x063A 0x063B 0x063C 0x06CD 0x063E 0x063F 0x0640 0x0641 0x0642 0x0643 0x0644 0x0645 0x0646 0x0647 0x0648 0x0649 0x064A 0x064B 0x064C 0x064D 0x064E 0x064F D7 D6 D5 D4 D3 R[23
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Data Sheet Addr Opt 1 Name 0x0650 R divider 0x0651 0x0652 0x0653 0x0654 S divider 0x0655 0x0656 0x0657 0x0658 Fractional feedback 0x0659 divider 0x065A 0x065B Lock detectors 0x065C 0x065D 0x065E 0x065F 0x0660 0x0661 0x0662 0x0663 0x0664 Unused to 0x067F Profile registers—Profile 2 0x0680 Priorities 0x0681 0x0682 0x0683 0x0684 0x0685 0x0686 0x0687 0x0688 0x0689 0x068A 0x068B 0x068C 0x068D 0x068E 0x068F 0x0690 0x0691 0x0692 0x0693 0x0694 0x0695 0x0696 0x0697 0x0698 0x0699 0x069A 0x069B 0x069C 0x069D AD9547 D
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AD9547 Data Sheet Addr Opt 1 Name 0x069E R divider 0x069F 0x06A0 0x06A1 0x06A2 S divider 0x06A3 0x06A4 0x06A5 0x06A6 Fractional feedback 0x06A7 divider 0x06A8 0x06A9 Lock detectors 0x06AA 0x06AB 0x06AC 0x06AD 0x06AE 0x06AF 0x06B0 0x06B1 Profile registers—Profile 3 0x06B2 Priorities 0x06B3 0x06B4 0x06B5 0x06B6 0x06B7 0x06B8 0x06B9 0x06BA 0x06BB 0x06BC 0x06BD 0x06BE 0x06BF 0x06C0 0x06C1 0x06C2 0x06C3 0x06C4 0x06C5 0x06C6 0x06C7 D6 D5 D4 D3 R[23:0] Unused D2 D1 D0 V[9:8] Def 0x00 0x00 0x00 0x00 0x0
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Data Sheet AD9547 Addr Opt 1 Name D7 D6 D5 D4 D3 D2 D1 D0 0x06D4 S divider S[15:0] 0x06D5 0x06D6 Unused S[19:16] 0x06D7 Unused 0x06D8 Fractional V[7:0] feedback 0x06D9 U[3:0] Unused V[9:8] divider 0x06DA Unused U[9:4] 0x06DB Lock Phase lock threshold[15:0] (in ps) detectors 0x06DC 0x06DD Phase lock fill rate[7:0] 0x06DE Phase lock drain rate[7:0] 0x06DF Frequency lock threshold[23:0] (in ps) 0x06E0 0x06E1 0x06E2 Frequency lock fill rate[7:0] 0x06E3 Frequency lock drain rate[7:0] 0x06E4 Unused to 0x06FF Pr
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AD9547 Data Sheet Addr Opt 1 Name D7 D6 D5 D4 D3 D2 User scratch pad (eight bytes) 0x0C00 Clock part Write user scratch pad[63:0] serial ID 0x0C01 0x0C02 0x0C03 0x0C04 0x0C05 0x0C06 0x0C07 Status readback (These registers are read only and are accessible during EEPROM transactions.
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Data Sheet Addr Opt 1 Name EEPROM storage sequence 0x0E10 E SYSCLK settings 0x0E11 E 0x0E12 0x0E13 0x0E14 E E E 0x0E15 0x0E16 0x0E17 0x0E18 0x0E19 0x0E1A 0x0E1B 0x0E1C 0x0E1D 0x0E1E 0x0E1F 0x0E20 0x0E21 0x0E22 0x0E23 0x0E24 0x0E25 0x0E26 0x0E27 0x0E28 0x0E29 0x0E2A 0x0E2B 0x0E2C 0x0E2D 0x0E2E 0x0E2F 0x0E30 0x0E31 0x0E32 0x0E33 0x0E34 to 0x0E3F E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E 1 AD9547 D7 D6 D5 D4 D3 Data: 9 bytes Address: 0x0100 I/O update SYSCLK calibration General
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AD9547 Data Sheet REGISTER BIT DESCRIPTIONS SERIAL PORT CONFIGURATION AND PART IDENTIFICATION (REGISTER 0x0000 TO REGISTER 0x0005) Table 38. SPI Control/I2 C Control Address 0x0000 Bit 7 Bit Name Unidirectional 6 LSB first/IncAddr 5 Soft reset 4 Long instruction [3:0] Unused Description Select SPI port SDO pin operating mode. 0 (default) = 3-wire. 1 = 4-wire (SDO pin enabled). Bit order for SPI port.
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Data Sheet AD9547 SYSTEM CLOCK (SYSCLK) (REGISTER 0x0100 TO REGISTER 0x0108) Table 44. Charge Pump and Lock Detect Control Address 0x0100 Bit 7 Bit Name External loop filter enable 6 Charge pump mode [5:3] Charge pump current 2 Lock detect timer disable [1:0] Lock detect timer Description Enables use of an external SYSCLK PLL loop filter. 0 (default) = internal loop filter. 1 = external loop filter. Charge pump current control. 0 (default) = automatic. 1 = manual.
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AD9547 Data Sheet Table 47. Nominal System Clock (SYSCLK) Period 1 Address 0x0103 0x0104 0x0105 1 Bit [7:0] [7:0] [7:5] [4:0] Bit Name Nominal SYSCLK period (expressed in fs) Unused Nominal SYSCLK period Description System clock period, Bits[7:0]. System clock period, Bits[15:8]. Unused. System clock period, Bits[20:16]. Units are femtoseconds (fs). The default value is 0x0F424 = 1,000,000 (1 ns) and implies a system clock frequency of 1 GHz. Table 48.
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Data Sheet AD9547 Register 0x0209 to Register 0x0210—IRQ Mask The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (Address 0x0D02 to Address 0x0D09). When set to Logic 1, the IRQ mask bits enable the corresponding IRQ monitor bits to indicate an IRQ event. The default for all IRQ mask bits is Logic 0, which prevents the IRQ monitor from detecting any internal interrupts. Table 51.
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AD9547 Data Sheet Table 55.
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Data Sheet AD9547 DPLL CONFIGURATION (REGISTER 0x0300 TO REGISTER 0x031B) Table 58. Free-Running Frequency Tuning Word 1 Address 0x0300 0x0301 0x0302 0x0303 0x0304 0x0305 1 Bit [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Bit Name Free-running frequency tuning word (expressed as a 48-bit frequency tuning word) Description Free-running frequency tuning word, Bits[7:0]. Free-running frequency tuning word, Bits[15:8]. Free-running frequency tuning word, Bits[23:16]. Free-running frequency tuning word, Bits[31:24].
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AD9547 Data Sheet Table 63. Incremental Closed-Loop Phase Lock Offset Step Size 1 Address 0x0314 0x0315 1 Bit [7:0] [7:0] Bit Name Incremental phase lock offset step size (expressed in ps/step) Description Incremental phase lock offset step size, Bits[7:0]. Incremental phase lock offset step size, Bits[15:8]. The default incremental closed loop phase lock offset step size value is 0x03E8 = 1000 (1 ns). Table 64.
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Data Sheet AD9547 CLOCK DISTRIBUTION OUTPUT CONFIGURATION (REGISTER 0x0400 TO REGISTER 0x0417) Table 67. Distribution Settings 1 Address 0x0400 1 Bit [7:6] 5 Bit Name Unused External distribution resistor 4 Receiver mode [3:2] 1 Unused OUT1 power-down 0 OUT0 power-down Description Unused. Output current control for the clock distribution outputs. 0 (default) = internal current setting resistor. 1 = external current setting resistor. Clock distribution receiver mode.
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AD9547 Data Sheet Table 71. Distribution Channel Modes Address 0x0404 0x0405 0x0406 0x0407 Bit [7:6] 5 Bit Name Unused OUT0 CMOS phase invert 4 OUT0 polarity invert 3 OUT0 drive strength [2:0] OUT0 mode [7:6] 5 Unused OUT1 CMOS phase invert 4 OUT1 polarity invert 3 OUT1 drive strength [2:0] OUT1 mode [7:0] [7:0] Unused Description Unused. When the output mode is CMOS, the bit inverts the relative phase between the two CMOS output pins. Otherwise, this bit is nonfunctional.
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Data Sheet AD9547 Register 0x0408 to Register 0x0417—Distribution Channel Dividers Table 72. Q0 Divider 1 Address 0x0408 0x0409 0x040A 0x040B 1 Bit [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name Q0 Unused Q0 Description Q0 divider, Bits[7:0]. Q0 divider, Bits[15:8]. Q0 divider, Bits[23:16]. Unused. Q0 divider, Bits[29:24]. The default value is 0 (or divide by 1). Table 73.
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AD9547 Data Sheet Table 76. Reference Logic Family Address 0x0501 0x0502 Bit [7:6] Bit Name Ref BB logic family [5:4] Ref B logic family [3:2] [1:0] [7:0] Ref AA logic family Ref A logic family Unused Description Select the logic family for the REF BB input receiver (ignored if Bits[5:4] = 00). 00 (default) = disabled. 01 = 1.2 V to 1.5 V CMOS. 10 = 1.8 V to 2.5 V CMOS. 11 = 3.0 V to 3.3 V CMOS. Select logic family for REF B input receiver.
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Data Sheet AD9547 PROFILE REGISTERS (REGISTER 0x0600 TO REGISTER 0x07FF) Note that the default value of every bit is 0 for Profile 0 to Profile 7. Register 0x0600 to Register 0x0631—Profile 0 Table 79. Priorities—Profile 0 Address 0x0600 Bit [7] Bit Name Phase lock scale [6] [5:3] Unused Promoted priority [2:0] Selection priority Description Controls the phase lock threshold unit scaling. 0 = picoseconds. 1 = nanoseconds. Unused.
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AD9547 Data Sheet Table 84.
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Data Sheet AD9547 Table 87. Fractional Feedback Divider—Profile 0 Address 0x0626 0x0627 0x0628 Bit [7:0] [7:4] [3:2] [1:0] [7:6] [5:0] Bit Name V U Unused V Unused U Description V, Bits[7:0]. U, Bits[3:0]. Unused. V, Bits[9:8]. Unused. U, Bits[9:4]. Table 88.
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AD9547 Address 0x063F Data Sheet Bit [7:4] [3:0] Bit Name Unused Outer tolerance Description Unused. Outer tolerance, Bits[19:16]. Table 92. Validation Timer—Profile 1 Address 0x0640 0x0641 Bit [7:0] [7:0] Bit Name Validation timer (expressed in units of ms) Description Validation timer, Bits[7:0]. Validation timer, Bits[15:8]. Table 93. Redetect Timer—Profile 1 Address 0x0642 0x0643 Bit [7:0] [7:0] Bit Name Redetect timer (expressed in units of ms) Description Redetect timer, Bits[7:0].
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Data Sheet AD9547 Table 96. S Divider—Profile 1 1 Address 0x0654 0x0655 0x0656 0x0657 1 Bit [7:0] [7:0] [7:4] [3:0] [7:0] Bit Name S S Unused S Unused Description S, Bits[7:0]. S, Bits[15:8]. Unused. S, Bits[19:16]. Unused. The value stored in the S divider register yields an actual divide ratio of one more than the programmed value. Furthermore, the value of S must be at least 7. Table 97.
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AD9547 Data Sheet Table 101. Tolerance—Profile 2 Address 0x0688 0x0689 0x068A 0x068B 0x068C 0x068D Bit [7:0] [7:0] [7:4] [3:0] [7:0] [7:0] [7:4] [3:0] Bit Name Inner tolerance Unused Inner tolerance Outer tolerance Unused Outer tolerance Description Inner tolerance, Bits[7:0]. Inner tolerance, Bits[15:8]. Unused. Inner tolerance, Bits[19:16]. Outer tolerance, Bits[7:0]. Outer tolerance, Bits[15:8]. Unused. Outer tolerance, Bits[19:16]. Table 102.
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Data Sheet AD9547 Register 0x069E to Register 0x06A8—Profile 2 Frequency Multiplication Table 105. R Divider—Profile 2 1 Address 0x069E 0x069F 0x06A0 0x06A1 1 Bit [7:0] [7:0] [7:0] [7:6] [5:0] Bit Name R Unused R Description R, Bits[7:0]. R, Bits[15:8]. R, Bits[23:16]. Unused. R, Bits[29:24]. The value stored in the R divider register yields an actual divide ratio of one more than the programmed value. Table 106.
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AD9547 Data Sheet Register 0x06B2 to Register 0x06FF—Profile 3 Table 109. Priorities—Profile 3 Address 0x06B2 Bit [7] Bit Name Phase lock scale [6] [5:3] Unused Promoted priority [2:0] Selection priority Description Controls the phase lock threshold unit scaling. 0 = picoseconds. 1 = nanoseconds. Unused. User assigned priority level (0 to 7) of the reference associated with Profile 3 while that reference is the active reference.
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Data Sheet Address 0x06C8 0x06C9 0x06CA 0x06CB 0x06CC 0x06CD 0x06CE 0x06CF 1 Bit [7:0] 7 [6:2] [1:0] [7:0] [7:0] [7:6] [5:1] 0 [7:0] 7 [6:0] [7:4] [3:0] AD9547 Bit Name Beta-0 linear Unused Beta-1 exponent Beta-0 linear Gamma-0 linear Unused Gamma-1 exponent Gamma-0 linear Delta-0 linear Delta-1 exponent Delta-0 linear Alpha-3 exponent Delta-1 exponent Description Beta-0 coefficient linear, Bits[14:7]. Unused. Beta-1 coefficient exponent, Bits[4:0]. Beta-0 coefficient linear, Bits[16:15].
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AD9547 Data Sheet Table 118. Lock Detectors—Profile 3 Address 0x06DB 0x06DC 0x06DD 0x06DE 0x06DF 0x06E0 0x06E1 0x06E2 0x06E3 0x06E4 to 0x06FF Bit [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Bit Name Phase lock threshold (units determined by Register 0x06B2[7]) Phase lock fill rate Phase lock drain rate Frequency lock threshold (expressed in units of ps) Frequency lock fill rate Frequency lock drain rate Unused Description Phase lock threshold, Bits[7:0].
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Data Sheet AD9547 Table 120. Loop Mode Address 0x0A01 Bit 7 6 Bit Name Unused User holdover 5 User free run [4:3] User selection mode 2 [1:0] Unused User reference selection Description Unused. Force the device into holdover mode. 0 (default) = normal operation. 1 = force device into holdover mode. The device functions as though all input references are faulted. Force the device into free-run mode. 0 (default) = normal operation. 1 = force device into free-run mode.
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AD9547 Data Sheet Register 0x0A03—Reset Functions Table 122. Reset Functions 1 Address 0x0A03 1 Bit 7 6 5 4 3 2 Bit Name Unused Clear LF Clear CCI Clear phase accumulator Reset auto sync Reset TW history 1 Reset all IRQs 0 Reset watchdog Description Unused. Setting this bit (default = 0) clears the digital loop filter (intended as a debug tool). Setting this bit (default = 0) clears the CCI filter (intended as a debug tool).
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Data Sheet AD9547 Table 126. IRQ Clearing for History Update, Frequency Limit, and Phase Slew Limit Address 0x0A07 Bit [7:5] 4 3 2 1 0 Bit Name Unused History updated Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Description Unused. Clears history updated IRQ. Clears frequency unclamped IRQ. Clears frequency clamped IRQ. Clears phase slew unlimited IRQ. Clears phase slew limited IRQ. Table 127.
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AD9547 Data Sheet Register 0x0A0E to Register 0x0A10—Reference Validation Override Controls Table 130. Force Validation Timeout 1 Address 0x0A0E 1 Bit [7:4] 3 Bit Name Unused Force Timeout BB 2 Force Timeout B 1 Force Timeout AA 0 Force Timeout A Description Unused. Setting this bit emulates timeout of the validation timer for Reference BB. This is an autoclearing bit. Setting this bit emulates timeout of the validation timer for Reference B. This is an autoclearing bit.
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Data Sheet AD9547 STATUS READBACK (REGISTER 0x0D00 TO REGISTER 0x0D19) All bits in Register 0x0D00 to Register 0x0D19 are read only. These registers are accessible during EEPROM transactions. Register 0x0D00 and Register 0x0D01 require an IO_UPDATE (Register 0x0005 = 0x01) in order to reflect their latest status. Table 134. EEPROM Status Address 0x0D00 Bit [7:3] 2 1 0 Bit Name Unused Fault detected Load in progress Save in progress Description Unused.
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AD9547 Data Sheet Table 139. IRQ Monitor for History Update, Frequency Limit, and Phase Slew Limit Address 0x0D05 Bit [7:5] 4 3 2 1 0 Bit Name Unused History updated Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Description Unused. Indicates the occurrence of a tuning word history update. Indicates a frequency limiter state transition from clamped to unclamped. Indicates a frequency limiter state transition from unclamped to clamped.
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Data Sheet AD9547 Table 142. Input Reference Status Address 0x0D0C 0x0D0D 0x0D0E 0x0D0F 0x0D10 0x0D11 0x0D12 0x0D13 Bit 7 [6:4] Bit Name Profile selected Selected profile 3 2 1 Valid Fault Fast 0 Slow [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Unused Description The control logic sets this bit when it assigns Ref A to one of the eight profiles. The index (0 to 7) of the profile assigned to Ref A. Note that these bits are meaningless unless Bit 7 = 1.
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AD9547 Data Sheet Table 146. Save Address 0x0E02 Bit [7:1] 0 Bit Name Unused Save to EEPROM Description Unused. Upload data to the EEPROM based on in the EEPROM storage sequence. This is an autoclearing bit. When an EEPROM save/load transfer is complete, wait a minimum of 10 μs before starting the next EEPROM save/load transfer. Table 147. Load Address 0x0E03 Bit [7:2] 1 0 Bit Name Unused Load from EEPROM Unused Description Unused. Download data from the EEPROM. This is an autoclearing bit.
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Data Sheet AD9547 Table 151. EEPROM Storage Sequence for DPLL Settings Address 0x0E18 Bit [7:0] Bit Name DPLL 0x0E19 0x0E1A [7:0] [7:0] DPLL Description The default value of this register is 0x1B, which the controller interprets as a data instruction. Its decimal value is 27, which tells the controller to transfer 28 bytes of data (27 + 1) beginning at the address specified by the next two bytes. The controller stores 0x1B in the EEPROM and increments the EEPROM address pointer.
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AD9547 Data Sheet Table 155. EEPROM Storage Sequence for Profile 2 and Profile 3 Settings Address 0x0E25 Bit [7:0] Bit Name Profile 2 and Profile 3 0x0E26 0x0E27 [7:0] [7:0] Profile 2 and Profile 3 Description The default value of this register is 0x63, which the controller interprets as a data instruction. Its decimal value is 99, which tells the controller to transfer 100 bytes of data (99 + 1), beginning at the address specified by the next two bytes.
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Data Sheet AD9547 Table 158. EEPROM Storage Sequence for Operational Control Settings Address 0x0E2F Bit [7:0] Bit Name Operational controls 0x0E30 0x0E31 [7:0] [7:0] Operational controls 0x0E32 [7:0] I/O update Description The default value of this register is 0x10, which the controller interprets as a data instruction. Its decimal value is 16, this tells the controller to transfer 17 bytes of data (16 + 1) beginning at the address specified by the next two bytes.
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AD9547 Data Sheet APPLICATIONS INFORMATION POWER SUPPLY PARTITIONS The AD9547 features multiple power supplies, and their power consumption varies with the AD9547 configuration. This section provides information about which power supplies can be grouped together and how the power consumption of each block varies with frequency. The numbers quoted in this section are for comparison only. Refer to the Specifications section for exact numbers.
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Data Sheet AD9547 CALCULATING THE DIGITAL FILTER COEFFICIENTS The digital loop filter coefficients (α, β, γ, and δ, as shown in Figure 39) relate to the time constants (T1, T2, and T3) that are associated with the equivalent analog circuit for a third-order loop filter (see Figure 66). Note that AD9547 evaluation software contains a profile designer that will compute these coefficients for you.
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AD9547 Data Sheet The min() function Calculation of the α Register Values The quantized α coefficient consists of four components: α0, α1, α2, and α3, according to y = min(x0, x1, ... xn) where: x0 through xn is a list of real numbers. y is the number in the list that is the farthest to the left on the number line. α ≈ αquantized = α0 × 2−16 − α The max() function y = max(x0, x1, ... xn) where: x0 through xn is a list of real numbers.
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Data Sheet AD9547 Calculation of the β Register Values Using the example value of −γ = 7.50373 × 10−5 yields The quantized β coefficient consists of two components, β0 and β1, according to −β ≈ βquantized = β0 × 2−(17 + β ) 1 x = 13, so γ1 = 13 y = 80570.6873700352, so γ0 = 80571 This leads to the following quantized value, which is very close to the desired value of 7.50373 × 10−5: where β0 and β1 are the register values.
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AD9547 Data Sheet OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.30 0.23 0.18 0.60 MAX 0.60 MAX 64 1 49 48 PIN 1 INDICATOR PIN 1 INDICATOR 8.85 8.75 SQ 8.65 0.50 BSC 0.50 0.40 0.30 33 32 PKG-1184 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 06-03-2013-C 0.05 MAX 0.02 NOM SEATING PLANE 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 16 17 BOTTOM VIEW TOP VIEW 1.