Datasheet

AD9540
Rev. A | Page 8 of 32
Parameter Min Typ Max Unit Test Conditions/Comments
51.84 MHz F
OUT
@ 10 Hz Offset 110 dBc/Hz
@ 100 Hz Offset 121 dBc/Hz
@ 1 kHz Offset 135 dBc/Hz
@ 10 kHz Offset 142 dBc/Hz
@ 100 kHz Offset 148 dBc/Hz
> 1 MHz Offset 153 dBc/Hz
105 MHz Analog Out
@ 10 Hz Offset 105 dBc/Hz
@ 100 Hz Offset 115 dBc/Hz
@ 1 kHz Offset 126 dBc/Hz
@ 10 kHz Offset 132 dBc/Hz
@ 100 kHz Offset 140 dBc/Hz
>1 MHz Offset 145 dBc/Hz
155.52 MHz Analog Out
@ 10 Hz Offset 100 dBc/Hz
@ 100 Hz Offset 112 dBc/Hz
@ 1 kHz Offset 123 dBc/Hz
@ 10 kHz Offset 131 dBc/Hz
@ 100 kHz Offset 138 dBc/Hz
>1 MHz Offset 144 dBc/Hz
1
The SNR of a 14-bit ADC was measured with an ENCODE rate of 105 MSPS and an AIN of 170 MHz. The resultant SNR was known to be limited by the jitter of the clock,
not by the noise on the AIN signal. From this SNR value, the jitter affecting the measurement can be back calculated.
2
Driving the REFIN input buffer. The crystal oscillator section of this input stage performs up to only 30 MHz.
3
The charge pump output compliance range is functionally 0.2 V to (CP_VDD − 0.2 V). The value listed here is the compliance range for 5% matching.
4
The input impedance of the CLK1 input is 1500 Ω. However, to provide matching on the clock line, an external 50 Ω load is used.
5
Measured as peak-to-peak between DAC outputs.
6
For a 4.02 kΩ resistor from DRV_RSET to GND.
7
Assumes a 1 mA load.
LOOP MEASUREMENT CONDITIONS
622 MHz OC-12 Clock
VCO = Sirenza 190-640T
Reference = Wenzel 500-10116 (30.3 MHz)
Loop Filter = 10 kHz BW, 60° Phase Margin
C1 = 170 nF, R1 = 14.4 Ω, C2 = 5.11 µF, R2 = 89.3 Ω,
C3 Omitted
CP_OUT = 4 mA (Scaler = ×8)
÷R = 2, ÷M = 1, ÷N = 1
105 MHz Converter Clock
VCO = Sirenza 190-845T
Reference = Wenzel 500-10116 (30.3 MHz)
Loop Filter = 10 kHz BW, 45° Phase Margin
C1 = 117 nF, R1 = 28 Ω, C2 = 1.6 µF, R2 = 57.1 Ω, C3 = 53.4 nF
CP_OUT = 4 mA (Scaler = ×8)
÷R = 8, ÷M = 1, ÷N = 1
C1
C3
INPUT OUTPUT
C2
R1
R2
04947-041
Figure 2. Generic Loop Filter