Datasheet

AD9540
Rev. A | Page 6 of 32
Parameter Min Typ Max Unit Test Conditions/Comments
CML OUTPUT DRIVER (OUT0)
Differential Output Voltage Swing
5
720 mV 50 Ω load to supply, both lines
Maximum Toggle Rate 655
Common-Mode Output Voltage 1.75 V
Output Duty Cycle 42 58 %
Output Current
Continuous
6
7.2 mA
Rising Edge Surge 20.9 mA
Falling Edge Surge 13.5 mA
Output Rise Time 250 ps 100 Ω terminated, 5 pF load
Output Fall Time 250 ps 100 Ω terminated, 5 pF load
LOGIC INPUTS (SDI/O, I/O_RESET, RESET,
I/O_UPDATE, S0, S1, S2, SYNC_IN)
V
IH
, Input High Voltage 2.0 V
V
IL
, Input Low Voltage 0.8 V
I
INH
, I
INL
, Input Current ±1 ±5 µA
C
IN
, Maximum Input Capacitance 3 pF
LOGIC OUTPUTS (SDO, SYNC_OUT, STATUS)
7
V
OH
, Output High Voltage 2.7 V
V
OH
, Output Low Voltage 0.4 V
I
OH
100 µA
I
OL
100 µA
POWER CONSUMPTION
Total Power Consumed, All Functions On 400 mW
I(AVDD) 85 mA
I(DVDD) 45 mA
I(DVDD_I/O) 20 mA
I(CP_VDD) 15 mA
Power-Down Mode 80 mW
WAKE-UP TIME (FROM POWER-DOWN MODE)
Digital Power-Down 12 ns Control Function Register 1[7]
DAC Power-Down 7 µs Control Function Register 3[39]
RF Divider Power-Down 400 ns Control Function Register 2[23]
Clock Driver Power-Down 6 µs Control Function Register 2[20]
Charge Pump Full Power-Down 10 µs Control Function Register 2[4]
Charge Pump Quick Power-Down 150 ns Control Function Register 2[3]
CRYSTAL OSCILLATOR (ON REFIN INPUT)
Operating Range 20 25 30 MHz
Residual Phase Noise (@ 25 MHz)
@ 10 Hz Offset 95 dBc/Hz
@ 100 Hz Offset 120 dBc/Hz
@ 1 kHz Offset 140 dBc/Hz
@ 10 kHz Offset 157 dBc/Hz
@ 100 kHz Offset 164 dBc/Hz
>1 MHz Offset 168 dBc/Hz
DIGITAL TIMING SPECIFICATIONS
CS
to SCLK Setup Time, T
PRE
6 ns
Period of SCLK (Write), T
SCLKW
40 ns
Period of SCLK (Read), T
SCLKR
400 ns
Serial Data Setup Time, T
DSU
6.5 ns
Serial Data Hold Time, T
DHD
0 ns
Data Valid Time, T
DV
40 ns