Datasheet

AD9540
Rev. A | Page 5 of 32
Parameter Min Typ Max Unit Test Conditions/Comments
F
IN
= 1966.08 MHz, F
OUT
= 491.52 MHz RF Divider R = 4
@ 10 Hz 105 dBc/Hz
@ 100 Hz 112 dBc/Hz
@ 1 kHz 122 dBc/Hz
@ 10 kHz 130 dBc/Hz
@ 100 kHz 141 dBc/Hz
@ 1 MHz 144 dBc/Hz
>3 MHz 146 dBc/Hz
F
IN
= 2488 MHz, F
OUT
= 622 MHz RF Divider R = 4
@ 10 Hz 100 dBc/Hz
@ 100 Hz 108 dBc/Hz
@ 1 kHz 115 dBc/Hz
@ 10 kHz 125 dBc/Hz
@ 100 kHz 135 dBc/Hz
@ 1 MHz 140 dBc/Hz
≥3 MHz 142 dBc/Hz
PHASE FREQUENCY DETECTOR/CHARGE PUMP
REFIN Input
Input Frequency
2
÷M Set to Divide by at Least 4 655 MHz
÷M Bypassed 200 MHz
Input Voltage Levels 200 450 600 mV p-p
Input Capacitance 10 pF
Input Resistance 1500 Ω
CLK2 Input
Input Frequency
÷N Set to Divide by at Least 4 655 MHz
÷N Bypassed 200 MHz
Input Voltage Levels 200 450 600 mV p-p
Input Capacitance 10 pF
Input Resistance 1500 Ω
Charge Pump Source/Sink Maximum Current 4 mA
Charge Pump Source/Sink Accuracy 5 %
Charge Pump Source/Sink Matching 2 %
Charge Pump Output Compliance Range
3
0.5 CP_VDD − 0.5 V
STATUS Drive Strength 2 mA
PHASE FREQUENCY DETECTOR NOISE FLOOR
@ 50 kHz PFD Frequency 148 dBc/Hz
@ 2 MHz PFD Frequency 133 dBc/Hz
@ 100 MHz PFD Frequency 116 dBc/Hz
@ 200 MHz PFD Frequency 113 dBc/Hz
RF DIVIDER (CLK1 ) INPUT SECTION (÷R)
RF Divider Input Range 1 2700 MHz
DDS SYSCLK not to
exceed 400 MSPS
Input Capacitance (DC) 3 pF
Input Impedance (DC) 1500 Ω
Input Duty Cycle 42 50 58 %
Input Power/Sensitivity −10 +4 dBm Single-ended, into a 50 Ω load
4
Input Voltage Level 200 1000 mV p-p