Datasheet

AD9540
Rev. A | Page 4 of 32
SPECIFICATIONS
AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± 5% (@ T
A
= 25°C), DAC_R
SET
= 3.92 kΩ, CP_R
SET
= 3.09 kΩ,
DRV_R
SET
= 4.02 kΩ, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
TOTAL SYSTEM JITTER AND PHASE NOISE FOR
105 MHz ADC CLOCK GENERATION CIRCUIT
Converter Limiting Jitter
1
720 f
S
rms
Resultant Signal-to-Noise Ratio (SNR) 59.07 dB
Phase Noise of Fundamental
@ 10 Hz Offset 80 dBc/Hz
@ 100 Hz Offset 92 dBc/Hz
@ 1 kHz Offset 101 dBc/Hz
@ 10 kHz Offset 110 dBc/Hz
@ 100 kHz Offset 147 dBc/Hz
≥1 MHz Offset 153 dBc/Hz
TOTAL SYSTEM PHASE NOISE FOR 210 MHz
ADC CLOCK GENERATION CIRCUIT
Phase Noise of Fundamental
@ 10 Hz Offset 79.2 dBc/Hz
@ 100 Hz Offset 86 dBc/Hz
@ 1 kHz Offset 95 dBc/Hz
@ 10 kHz Offset 105 dBc/Hz
@ 100 kHz Offset 144 dBc/Hz
@ 1 MHz Offset 151 dBc/Hz
TOTAL SYSTEM TIME JITTER FOR CLOCKS
155.52 MHz Clock 581 f
S
rms 12 kHz to 1.3 MHz bandwidth
622.08 MHz Clock 188 f
S
rms 12 kHz to 5 MHz bandwidth
RF DIVIDER/CML DRIVER EQUIVALENT
INTRINSIC TIME JITTER
F
IN
= 414.72 MHz, F
OUT
= 51.84 MHz 136 f
S
rms R = 8, BW = 12 kHz to 400 kHz
F
IN
= 1244.16 MHz, F
OUT
= 155.52 MHz 101 f
S
rms R = 8, BW = 12 kHz to 1.3 MHz
F
IN
= 2488.32 MHz, F
OUT
= 622.08 MHz 108 f
S
rms R = 4, BW = 12 kHz to 5 MHz
RF DIVIDER/CML DRIVER RESIDUAL PHASE NOISE
F
IN
= 81.92 MHz, F
OUT
= 10.24 MHz RF Divider R = 8
@ 10 Hz 120 dBc/Hz
@ 100 Hz 128 dBc/Hz
@ 1 kHz 137 dBc/Hz
@ 10 kHz 145 dBc/Hz
@ 100 kHz 150 dBc/Hz
≥1 MHz 153 dBc/Hz
F
IN
= 983.04 MHz, F
OUT
= 122.88 MHz RF Divider R = 8
@ 10 Hz 115 dBc/Hz
@ 100 Hz 125 dBc/Hz
@ 1 KHz 132 dBc/Hz
@ 10 kHz 142 dBc/Hz
@ 100 kHz 146 dBc/Hz
@ 1 MHz 151 dBc/Hz
>3 MHz 153 dBc/Hz