Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- PRODUCT OVERVIEW
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- TYPICAL PERFORMANCE CHARACTERISTICS
- TYPICAL APPLICATION CIRCUITS
- THEORY OF OPERATION
- MODES OF OPERATION
- SERIAL PORT OPERATION
- REGISTER MAP AND DESCRIPTION
- OUTLINE DIMENSIONS

AD9540
Rev. A | Page 16 of 32
FREQUENCY (Hz)
L(f) (dBc/Hz)
0
–10
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–30
–40
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10 1k100 10k 100k 10M1M
04947-035
Figure 28. RF Divider and CML Driver Residual
Phase Noise (2488 MHz In, 622 MHz Out)
FREQUENCY (Hz)
L(f) (dBc/Hz)
0
–10
–20
–30
–40
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–50
–70
–80
–90
–100
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–130
–120
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–170
10 1k100 10k 100k 1M 20M
04947-0-036
Figure 29. Total System Phase Noise for 105 MHz Converter Clock
FREQUENCY (Hz)
L(f) (dBc/Hz)
0
–10
–20
–30
–40
–60
–50
–70
–80
–90
–100
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–130
–120
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10 1k100 10k 100k 1M 20M
04947-0-037
Figure 30. Total System Phase Noise for 210 MHz Converter Clock
FREQUENCY (Hz)
L(f) (dBc/Hz)
0
–10
–20
–30
–40
–60
–50
–70
–80
–90
–100
–110
–130
–120
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10 1k100 10k 100k 1M 20M
04947-0-038
Figure 31. Total System Phase Noise for 622 MHz OC-12 Clock