Datasheet

AD9540
Rev. A | Page 10 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13 14 15 16 17 18 19 20
21
22 23 24
SDO
SDI/O SCLK
CS
DVDD_I/O
SYNC_OUT
SYNC_IN/STATUS
I/O_UPDATE
S0 S1 S2
DGND
48 47 46 45 44 43 42 41 40 39 38 37
AVDD DAC_RSE
T
DRV_RSET CP_RSET AVDD AGND CLK2 CLK2 REFIN REFIN AVDD AGND
1
2
3
4
5
6
7
8
9
10
11
12
AGND
AVDD
AGND
AVDD
IOUT
IOUT
AVDD
AGND
I/O_RESET
RESET
DVDD
DGND
CP_VDD
AGND
OUT0
OUT0
CP_VDD
AGND
CLK1
CLK1
AVDD
AGND
DVDD
35
CP_OUT36
34
33
32
31
30
29
28
27
26
25
AD9540
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
04947-047
Figure 3. 48-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 3, 8, 26, 30,
34, 37, 43,
AGND Analog Ground.
2, 4, 7, 27, 38,
44, 48
AVDD Analog Core Supply (1.8 V).
5 IOUT DAC Analog Output.
6
IOUT
DAC Analog Complementary Output.
9 I/O_RESET
Resets the serial port when synchronization is lost in communications but does not reset the
device itself (active high). When not being used, this pin should be forced low, because it floats to
the threshold value.
10 RESET Master Reset. Clears all accumulators and returns all registers to their default values (active high).
11, 25 DVDD Digital Core Supply (1.8 V).
12, 24 DGND Digital Ground.
13 SDO Serial Data Output. Used only when the device is programmed for 3-wire serial data mode.
14 SDI/O
Serial Data Input/Output. When the part is programmed for 3-wire serial data mode, this is input
only; in 2-wire mode, it serves as both the input and output.
15 SCLK Serial Data Clock. Provides the clock signal for the serial data port.
16
CS Active Low Signal That Enables Shared Serial Buses. When brought high, the serial port ignores the
serial data clocks.
17 DVDD_I/O Digital Interface Supply (3.3 V).
18 SYNC_OUT Synchronization Clock Output.
19 SYNC_IN/STATUS
Bidirectional Dual Function Pin. Depending on device programming, this pin is either the direct
digital synthesizer’s (DDS) synchronization input (allows alignment of multiple subclocks), or the PLL
lock detect output signal.
20 I/O_UPDATE
This input pin, when set high, transfers the data from the I/O buffers to the internal registers on the
rising edge of the internal SYNC_CLK, which can be observed on SYNC_OUT.