Datasheet

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655 MHz Low Jitter Clock Generator

AD9540

Rev. A

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FEATURES

Excellent intrinsic jitter performance

200 MHz phase frequency detector inputs

655 MHz programmable input dividers for the phase

frequency detector (÷M, ÷N) {M, N = 1 to 16} (bypassable)

Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)

8 programmable phase/frequency profiles

400 MSPS internal DDS clock speed

48-bit frequency tuning word resolution

14-bit programmable phase offset

1.8 V supply for device operation

3.3 V supply for I/O, CML driver, and charge pump output

Software controlled power-down

48-lead LFCSP_VQ package

Programmable charge pump current (up to 4 mA)

Dual-mode PLL lock detect

655 MHz CML-mode PECL-compliant output driver

APPLICATIONS

Clocking high performance data converters

Base station clocking applications

Network (SONET/SDH) clocking

Gigabit Ethernet (GbE) clocking

Instrumentation clocking circuits

Agile LO frequency synthesis

Automotive radar

FM chirp source for radar and scanning systems

Test and measurement equipment

Acousto-optic device drivers

FUNCTIONAL BLOCK DIAGRAM

AVDD AGND DVDD DGND CP_VDD CP_RSET

REF, AMP

REFIN

CLK1

CHARGE

PUMP

PHASE

FREQUENCY

DETECTOR

M DIVIDER

N DIVIDER

DIVIDER

1, 2, 4, 8

SYNC_IN/STATUS

SYNC, PLL

LOCK

SCLK

SDI/O

SDO

SERIAL

CONTROL

PORT

TIMING AND

CONTROL LOGIC

CLK2

CP_OUT

CLK2

DRV_RSE

OUT0

CML

OUT0

CLK

DIVCLK

PHASE/

FREQUENCY

PROFILES

DDS

IOUT

DAC

DAC_RSET

04947-001

AD9540

Figure 1.

Summary of content (32 pages)

PAGE 1
655 MHz Low Jitter Clock Generator AD9540 FEATURES APPLICATIONS Excellent intrinsic jitter performance 200 MHz phase frequency detector inputs 655 MHz programmable input dividers for the phase frequency detector (÷M, ÷N) {M, N = 1 to 16} (bypassable) Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable) 8 programmable phase/frequency profiles 400 MSPS internal DDS clock speed 48-bit frequency tuning word resolution 14-bit programmable phase offset 1.8 V supply for device operation 3.
PAGE 2
AD9540 TABLE OF CONTENTS Features .............................................................................................. 1 CML Driver................................................................................. 19 Applications....................................................................................... 1 DDS and DAC ............................................................................ 20 Functional Block Diagram ..............................................................
PAGE 3
AD9540 PRODUCT OVERVIEW The AD9540 is Analog Devices’ first dedicated clocking product specifically designed to support the extremely stringent clocking requirements of the highest performance data converters. The device features high performance PLL (phaselocked loop) circuitry, including a flexible 200 MHz phase frequency detector and a digitally controlled charge pump current. The device also provides a low jitter, 655 MHz CMLmode, PECL-compliant output driver with programmable slew rates.
PAGE 4
AD9540 SPECIFICATIONS AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± 5% (@ TA = 25°C), DAC_RSET = 3.92 kΩ, CP_RSET = 3.09 kΩ, DRV_RSET = 4.02 kΩ, unless otherwise noted. Table 1.
PAGE 5
AD9540 Parameter FIN = 1966.08 MHz, FOUT = 491.
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AD9540 Parameter CML OUTPUT DRIVER (OUT0) Differential Output Voltage Swing5 Maximum Toggle Rate Common-Mode Output Voltage Output Duty Cycle Output Current Continuous6 Rising Edge Surge Falling Edge Surge Output Rise Time Output Fall Time LOGIC INPUTS (SDI/O, I/O_RESET, RESET, I/O_UPDATE, S0, S1, S2, SYNC_IN) VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL, Input Current CIN, Maximum Input Capacitance LOGIC OUTPUTS (SDO, SYNC_OUT, STATUS)7 VOH, Output High Voltage VOH, Output Low Voltage IOH IOL
PAGE 7
AD9540 Parameter I/O_Update to SYNC_OUT Setup Time PS[2:0> to SYNC_OUT Setup Time Latencies/Pipeline Delays I/O_Update to DAC Frequency Change I/O_Update to DAC Phase Change PS[2:0] to DAC Frequency Change PS[2:0] to DAC Phase Change I/O_Update to CP_OUT Scaler Change I/O_Update to Frequency Accumulator Step Size Change DAC OUTPUT CHARACTERISTICS Resolution Full-Scale Output Current Gain Error Output Offset Output Capacitance Voltage Compliance Range Wideband SFDR (DC to Nyquist) 10 MHz Analog Out 40 MHz An
PAGE 8
AD9540 Parameter 51.84 MHz FOUT @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset > 1 MHz Offset 105 MHz Analog Out @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset 155.
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AD9540 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Digital I/O Supply Voltage (DVDD_I/O) Charge Pump Supply Voltage (CP_VDD) Maximum Digital Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Thermal Resistance (θJA) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 10
AD9540 48 47 46 45 44 43 42 41 40 39 38 37 AVDD DAC_RSET DRV_RSET CP_RSET AVDD AGND CLK2 CLK2 REFIN REFIN AVDD AGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND AVDD 1 2 PIN 1 INDICATOR AGND 3 AVDD 4 IOUT 5 IOUT 6 AVDD 7 AGND 8 I/O_RESET 9 RESET 10 DVDD 11 DGND 12 AD9540 CP_OUT CP_VDD AGND OUT0 OUT0 CP_VDD AGND CLK1 CLK1 AVDD AGND DVDD 04947-047 SDO SDI/O SCLK CS DVDD_I/O SYNC_OUT SYNC_IN/STATUS I/O_UPDATE S0 S1 S2 DGND 13 14 15 16 17 18 19 20 21 22 23 24 TOP VIEW (Not to Scale) 36 35 34 3
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AD9540 Pin No. 21, 22, 23 Mnemonic S0, S1, S2 28 29 31, 35 32 33 36 39 40 41 42 45 46 47 Paddle CLK1 CLK1 CP_VDD OUT0 OUT0 CP_OUT REFIN REFIN CLK2 CLK2 CP_RSET DRV_RSET DAC_RSET Exposed Paddle Description Clock Frequency and Delay Select Pins. These pins specify one of eight clock frequency/delay profiles. RF Divider and Internal Clock Complementary Input. RF Divider and Internal Clock Input. Charge Pump and CML Driver Supply Pin. 3.3 V analog (clean) supply. CML Driver Complementary Output.
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AD9540 TYPICAL PERFORMANCE CHARACTERISTICS REF LVL 0dBm RBW 100Hz VBW 100Hz 25s SWT DELTA 1 [T1] –85.94dB –2.10420842kHz 0 RF ATT 20dB UNIT 0 1 –10 –20 –20 –30 RF ATT 20dB UNIT dB 1 A –10 RBW 100Hz VBW 100Hz 25s SWT DELTA 1 [T1] –84.94dB 2.10420842kHz REF LVL 0dBm dB A –30 1 AP 1 AP –40 –40 –50 –50 –60 –60 –70 –70 –80 1 –90 –100 CENTER 10.1MHz 5kHz/ –100 SPAN 50kHz CENTER 40.1MHz Figure 4.
PAGE 13
AD9540 REF LVL 0dBm RBW 100Hz VBW 100Hz 25s SWT DELTA 1 [T1] –83.72dB –2.70541082kHz 0 RF ATT 20dB UNIT REF LVL 0dBm dB RBW 100Hz VBW 100Hz 25s SWT DELTA 1 [T1] –85.98dB –2.90581162kHz RF ATT 20dB UNIT dB 0 1 1 A –10 –10 –20 –20 –30 A –30 1 AP 1 AP –40 –40 –50 –50 –60 –60 –70 –70 –80 04947-009 1 –90 –100 CENTER 100.1MHz 5kHz/ –90 RBW 500Hz VBW 500Hz 20s SWT DELTA 1 [T1] –56.47dB –400.80160321kHz 0 1 –100 SPAN 50kHz CENTER 159.5MHz Figure 10.
PAGE 14
100k 1M L(f) (dBc/Hz) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 L(f) (dBc/Hz) 100 1k 10k 100k FREQUENCY (Hz) 1M 10k 100k FREQUENCY (Hz) 1M 10M 100 1k 10k FREQUENCY (Hz) 100k 1M 2M Figure 20. RF Divider and CML Driver Residual Phase Noise (81.92 MHz In, 10.24 MHz Out) 04947-025 L(f) (dBc/Hz) Figure 17.
PAGE 15
10k 100k FREQUENCY (Hz) 1M 10M L(f) (dBc/Hz) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 L(f) (dBc/Hz) 100 1k 10k 100k FREQUENCY (Hz) 1M 10k 100k FREQUENCY (Hz) 1M 10M 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 26. RF Divider and CML Driver Residual Phase Noise (1680 MHz In, 210 MHz Out) 04947-031 L(f) (dBc/Hz) Figure 23.
PAGE 16
1k 10k 100k FREQUENCY (Hz) 1M 10M L(f) (dBc/Hz) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 10 100 1k 10k 100k FREQUENCY (Hz) 1M 1k 10k 100k FREQUENCY (Hz) 1M 20M Figure 30. Total System Phase Noise for 210 MHz Converter Clock 04947-0-036 L(f) (dBc/Hz) Figure 28. RF Divider and CML Driver Residual Phase Noise (2488 MHz In, 622 MHz Out) 100 20M Figure 29. Total System Phase Noise for 105 MHz Converter Clock Rev.
PAGE 17
AD9540 TYPICAL APPLICATION CIRCUITS 25MHz CRYSTAL PHASE FREQUENCY DETECTOR/CHARGE PUMP ÷M REFIN ÷N CLK2 400MHz CP_OUT VCO LPF CML DRIVER ÷R DAC DDS CLOCK1′ LPF ADCMP563 Figure 32. Dual Clock Configuration PHASE FREQUENCY DETECTOR 622MHz CHARGE PUMP CLK2 VCO LPF CML DRIVER ÷R CLOCK1 AD9540 DAC DDS CLOCK2 ADCMP563 Figure 33.
PAGE 18
AD9540 DDS CML DRIVER 8-LEVEL FSK (FC = 100MHz) DAC BPF ÷R AD9540 BPF REFIN 25MHz CRYSTAL CP_OUT CLK2 2.5GHz TONE LPF 04947-046 ÷N VCO Figure 36. ISM Band Modulator (LO & Baseband Generation) APPLICATION CIRCUIT DESCRIPTIONS Dual Clock Configuration In this loop, M = 1, N = 16, and R = 4. The DDS (direct digital synthesizer) tuning word is also equal to ¼, so that the frequency of CLOCK1’ equals the frequency of CLOCK 1.
PAGE 19
AD9540 THEORY OF OPERATION PLL CIRCUITRY CML DRIVER The AD9540 includes an RF divider (divide-by-R), a 48-bit DDS core, a 14-bit programmable delay adjustment, a 10-bit DAC (digital-to-analog converter), a phase frequency detector, and a programmable output current charge pump. Incorporating these blocks together, users can generate many useful circuits for clock synthesis. A few simple examples are shown in the Typical Performance Characteristics section.
PAGE 20
AD9540 DDS AND DAC The precision frequency division within the device is accomplished using DDS technology. The DDS can control the digital phase relationships by clocking a 48-bit accumulator. The incremental value loaded into the accumulator, known as the frequency tuning word, controls the overflow rate of the accumulator.
PAGE 21
AD9540 MODES OF OPERATION Automatic Synchronization SELECTABLE CLOCK FREQUENCIES AND SELECTABLE EDGE DELAY Because the precision driver is implemented using a DDS, it is possible to store multiple clock frequency words to enable externally switchable clock frequencies. The phase accumulator runs at a fixed frequency, according to the active profile clock frequency word. Likewise, any delay applied to the rising and falling edges is a static value that comes from the delay shift word of the active profile.
PAGE 22
AD9540 SERIAL PORT OPERATION An AD9540 serial data port communication cycle has two phases. Phase 1 is the instruction cycle, writing an instruction byte to the AD9540, coincident with the first eight SCLK rising edges. The instruction byte provides the AD9540 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle.
PAGE 23
AD9540 INSTRUCTION BYTE MSB/LSB TRANSFERS The instruction byte contains the following information. The AD9540 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the LSB first bit in Control Register 1 (CFR1[15]). The default value of this bit is low (MSB first). When CFR1[15] is set high, the AD9540 serial port is in LSB first format. The instruction byte must be written in the format indicated by CFR1[15].
PAGE 24
AD9540 REGISTER MAP AND DESCRIPTION Table 4. Register Map Register Name (Serial Address) Control Function Register 1 (CFR1) (0x00) Control Function Register 2 (CFR2) (0x01) Bit Range [31:24] [23:16] Bit 6 Open1 AutoClear Freq. Accum. SDI/O Input Only PFD Input PowerDown Open1 Bit 5 Open1 AutoClear Phase Accum. Open1 Bit 4 Open1 Enable Sine Output Bit 3 Open1 Clear Freq. Accum. Bit 2 Open1 Clear Phase Accum.
PAGE 25
AD9540 Register Name (Serial Address) Profile Control Register 0 (PCR0) (0x06) Profile Control Register 1 (PCR1) (0x07) Profile Control Register 2 (PCR2) (0x08) Profile Control Register 3 (PCR3) (0x09) Profile Control Register 4 (PCR4) (0x0A) Profile Control Register 5 (PCR5) (0x0B) Bit Range [63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] [63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] [63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] [63:56] [55:48] [47:40] [39:3
PAGE 26
AD9540 Register Name (Serial Address) Profile Control Register 6 (PCR6) (0x0C) Profile Control Register 7 (PCR7) (0x0D) 1 Bit Range [63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] [63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] Bit 7 (MSB) Bit 6 1 Open Open1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Phase Offset Word 6 (POW6) [13:8] Phase Offset Word 6 (POW6) [7:0] Frequency Tuning Word 6 (FTW6) [47:40] Frequency Tuning Word 6 (FTW6) [39:32] Frequency Tuning Word 6 (FTW6) [31:24] Frequ
PAGE 27
AD9540 CFR1[22] = 0 (default). Issuing an I/O_UPDATE has no effect on the current state of the frequency accumulator. CONTROL REGISTER BIT DESCRIPTIONS Control Function Register 1 (CFR1) This control register is comprised of four bytes that must be written during a write operation involving CFR1. CFR1 is used to control various functions, features, and operating modes of the AD9540. The functionality of each bit is described below.
PAGE 28
AD9540 CFR1[15] = 0 (default). Serial data transfer to the device is in MSB first mode. CFR1[15] = 1. Serial data transfer to the device is in LSB first mode. CFR1[14] SDI/O Input Only (3-Wire Serial Data Mode) The serial port on the AD9540 can act in 2-wire mode (SCLK and SDI/O) or 3-wire mode (SCLK, SDI/O, and SDO). This bit toggles the serial port between these two modes.
PAGE 29
AD9540 CFR1[1] = 0 (default). The hardware manual synchronization function is disabled. Either the part is outputting the STATUS (CFR1[3] = 0) or it is using the SYNC_IN to slave the SYNC_CLK signal to an external reference provided on SYNC_IN (CFR1[3] = 1). CFR1[1] = 1. The SYNC_IN/STATUS pin is set as a digital input. Each subsequent rising edge on this pin advances the SYNC_CLK rising edge by one SYSCLK period. CFR2[32] = 0 (default).
PAGE 30
AD9540 CFR2[24] = 0 (default). The lock detect acts as a status indicator (PLL is locked 0 or unlocked 1). This bit disables all slew rate enhancement surge current, including the default values. CFR2[24] = 1. The lock detect acts as a lead-lag indicator. A 1 on the STATUS pin means that the CLK2 pin lags the reference. A 0 means that the CLK2 pin leads the reference. CFR2[17] = 0 (default). The CML driver applies default surge current to rising and falling edges.
PAGE 31
AD9540 CFR2[7:6] Open CFR2[3] Charge Pump Quick Power-Down Unused locations. Write a Logic 0. Rather than power down the charge pump, which have a long recovery time, a quick power-down mode that powers down only the charge pump output buffer is included. Though this does not reduce the power consumption significantly, it does shut off the output to the charge pump and allows it to come back on rapidly.
PAGE 32
AD9540 OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR TOP VIEW 48 1 5.25 5.10 SQ 4.95 (BOTTOM VIEW) 25 24 12 13 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP 12° MAX PIN 1 INDICATOR EXPOSED PAD 6.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 0.30 0.23 0.18 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 45.