Datasheet

Data Sheet AD9525
Rev. A | Page 7 of 48
TIMING CHARACTERISTICS
Table 10.
Parameter Min Typ Max Unit Test Conditions/Comments
PROPAGATION DELAY, t
PECL
, CLKIN TO LVPECL OUTPUT Termination as shown in Figure 35
For All M Divider Values 461 522 600 ps High frequency clock distribution configuration
Variation with Temperature 388 fs/°C
OUTPUT SKEW, LVPECL OUTPUTS
1
All LVPECL Outputs 13.5 25.2 ps Across temperature and VDD per device
Temperature Coefficient 14 fs/°C
All LVPECL Outputs Across Multiple Parts 144 ps
OUTPUT SKEW, LVPECL-TO-SYNC_OUT
1
SYNC_OUT LVPECL Mode
All LVPECL Outputs 189 298 ps Across temperature and VDD per device
Temperature Coefficient 543 fs/°C
All LVPECL Outputs Across Multiple Parts 417 ps
SYNC_OUT CMOS Mode
All LVPECL Outputs 1.64 2.34 ns Across temperature and VDD per device
All LVPECL Outputs Across Multiple Parts 2.46 ns
PROPAGATION DELAY, REF TO LVPECL OUTPUT 267 581 924 ps
REF refers to either REFA/REFA
or REFB/REFB pairs
1
The output skew is the difference between any two paths while operating at the same voltage and temperature.
Timing Diagrams
CLK
t
CMOS
t
CLK
t
PECL
10011-002
Figure 2. CLK/
CLK
to Clock Output Timing, M Divider = 1
DIFFERENTIAL
LVPECL
80%
20%
t
RP
t
FP
10011-003
Figure 3. LVPECL Timing, Differential