Datasheet

AD9525 Data Sheet
Rev. A | Page 6 of 48
PLL DIGITAL LOCK DETECT
Table 8.
Parameter Min Typ Max Unit Test Conditions/Comments
PLL DIGITAL LOCK DETECT WINDOW
1
Signal available at the STATUS and REF_MON pins when
selected by appropriate register settings; lock detect window
settings can be varied by changing the CPRSET resistor
Lock Threshold (Coincidence of Edges)
Selected by Reg. 0x010[1:0] and Reg. 0x019[1], which is the
threshold for transitioning from unlock to lock
Low Range (ABP 1.3 ns, 2.9 ns) 4 ns Reg. 0x010[1:0] = 00b, 01b,11b; Reg. 0x019[1] = 1b
High Range (ABP 1.3 ns, 2.9 ns) 7 ns Reg. 0x010[1:0] = 00b, 01b, 11b; Reg. 0x019[1] = 0b
High Range (ABP 6.0 ns) 3.5 ns Reg. 0x010[1:0] = 10b; Reg. 0x019[1] = 0b
Unlock Threshold (Hysteresis)
1
Selected by Reg. 0x017[1:0] and Reg. 0x019[1], which is the
threshold for transitioning from unlock to lock
Low Range (ABP 1.3 ns, 2.9 ns) 8.3 ns Reg. 0x010[1:0] = 00b, 01b, 11b; Reg. 0x019[1] = 1b
High Range (ABP 1.3 ns, 2.9 ns) 16.9 ns Reg. 0x010[1:0] = 00b, 01b, 11b; Reg. 0x019[1] = 0b
High Range (ABP 6.0 ns) 11 ns Reg. 0x010[1:0] = 10b; Reg. 0x019[1] = 0b
1
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
CLOCK OUTPUTS
Table 9.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL CLOCK OUTPUTS
Output Frequency, Maximum 3.6 GHz
Rise Time/Fall Time (20% to 80%) 105 162 ps
Duty Cycle Input duty cycle = 50/50
M = 1 47 50 53 % FOUT = 2800 MHz
45 50 55 % FOUT < 3000 MHz
M = 2, 4, 6
47
49
51
%
FOUT = 1400 MHz
45 49 55 % FOUT < 1500 MHz
M = 3, 5 32 32 33 % FOUT = 933.33 MHz
Output Differential Voltage,
Magnitude
750 830 984 mV Voltage across pins, output driver static;
Termination = 50 Ω to VDD3 − 2 V
Common-Mode Output Voltage
VDD3 –
1.42
VDD3 –
1.37
VDD3 –
1.32
V
Output driver static; VDD3 (Pin 3, Pin 36, Pin 41, Pin 46);
Termination = 50 Ω to VDD3 − 2 V