Datasheet

AD9525 Data Sheet
Rev. A | Page 40 of 48
Table 38. PLL Readback
Reg.
Addr.
(Hex) Bits Bit Name Description
0x01F
[7:5]
Unused
Unused
4 Selected reference
Shows the reference used by the PLL
0: REFA
1: REFB
3 Status feedback clock Status of the feedback clock, does not have a valid output unless 0x01A[7] = 1
0: missing
1: present
2 Status REFB
Status of Reference B clock, does not have a valid output unless 0x01A[5] = 1 and
0x01C[5] = 0
0: missing
1: present
1
Status REFA
Status of Reference A clock, does not have a valid output unless 0x01A[6] = 1 and
0x01C[4] = 0
0: missing
1: present
0 Digital lock detect (DLD) Digital lock detect
0: PLL not locked
1: PLL locked
Table 39. LVPECL Drivers OUT0
Reg.
Addr.
(Hex)
Bits Bit Name Description
0x0F0 [7:5] Don’t care Don’t care
4
Power down Channel 0 and
Channel 1
Powers down Channel 0 and Channel 1
0: enabled (default)
1: power-down
3
Don’t care
Don’t care
[2:1] OUT0 level
Bit 1 Bit 0 V
OD
(mV)
0 0 400
0 1 600
1 0 780 (default)
1 1 960
0 OUT0 driver power-down
0: enabled (default)
1: power-down
Table 40. LVPECL Drivers OUT1
Reg.
Addr.
(Hex) Bits Bit Name Description
0x0F1 [7:5] Don’t care Don’t care
4 Reserved Reserved, write 0
3 Don’t care Don’t care
[2:1] OUT1 level
Bit 1 Bit 0 V
OD
(mV)
0
0
400
0 1 600
1 0 780 (default)
1 1 960
0 OUT1 driver power-down 0: enabled (default)
1: power-down