Datasheet

AD9525 Data Sheet
Rev. A | Page 36 of 48
Reg.
Addr.
(Hex) Bits Bit Name Description
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Level or
Dynamic
Signal Signal at STATUS Pin
1 0 1 0 1 0 LVL
(DLD) AND (selected reference present)
AND (feedback clock present).
1 0 1 0 1 1 LVL Feedback clock present (active high).
1 0 1 1 0 0 LVL Selected reference (low: REFA, high: REFB).
1
0
1
1
0
1
LVL
DLD; active high.
1 0 1 1 1 0 LVL N/A.
1 0 1 1 1 1 LVL Ground (dc).
1 1 0 0 0 0 LVL VDD3 (PLL power supply).
1 1 0 0 0 1 DYN
REFA clock.
1 1 0 0 1 0 DYN
REFB clock.
1 1 0 0 1 1 DYN
Selected reference to PLL.
1 1 0 1 0 0 DYN
Unselected reference to PLL.
1 1 0 1 0 1 LVL
Status of selected reference (status of
differential reference); active low.
1 1 0 1 1 0 LVL Both reference clocks missing; active low.
1
1
0
1
1
1
LVL
REFA present (active low).
1 1 1 0 0 0 LVL REFB present (active low).
1 1 1 0 0 1 LVL
(REFA present) AND (REFB present).
1 1 1 0 1 0 LVL
(DLD) AND (selected reference present)
AND (feedback clock present); (active low).
1 1 1 0 1 1 LVL
Feedback clock present
1 1 1 1 0 0 LVL
Selected reference (low = REFA, high =
REFB); active low.
1 1 1 1 0 1 LVL DLD (active low).
1 1 1 1 1 0 LVL N/A.
1 1 1 1 1 1 LVL VDD3 (PLL power supply).