Datasheet

Data Sheet AD9525
Rev. A | Page 35 of 48
Reg.
Addr.
(Hex) Bits Bit Name Description
2 REFB divider reset Resets REFB divider.
0: normal (default).
1: holds REFB divider in reset.
1 REFA divider reset Resets REFA divider.
0: normal (default).
1: holds REFA divider in reset.
0
Reset all dividers
Resets REFA, REFB, B divider (B divider is part of N divider).
0: normal (default).
1: holds REFA, REFB, B divider in reset.
0x016
7
REFC enable
Enables REFC path.
0: disabled (default).
1: enables REFC path.
[6:0]
REFC divider
7-bit REFC divider. Divide-by-1 to divide-by-127.
0000000, 0000001: both divide-by-1 (default: 0x00).
Table 32. Status Pin and Other
Reg.
Addr.
(Hex)
Bits Bit Name Description
0x017
7
Charge pump pin
to VDD_CP/2
Sets the charge pump pin to one-half of the VDD_CP supply voltage.
0: charge pump normal operation (default).
1: charge pump pin set to VDD_CP/2.
6
STATUS pin divider
enable
Enables STATUS pin divider.
0: disabled (default).
1: enables divider.
[5:0]
STATUS output
select
Selects the signal that appears at the STATUS pin. Register 0x017[6] must be set to 0 to for any mode
identified as LVL.
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Level or
Dynamic
Signal Signal at STATUS Pin
0 0 0 0 0 0 LVL Ground, dc (default).
0 0 0 0 0 1 DYN N divider output.
0 0 0 0 1 0 LVL Ground, dc.
0 0 0 0 1 1 LVL Ground, dc.
0 0 0 1 0 0 LVL Ground, dc.
0 0 0 1 0 1 DYN PFD up pulse.
0 0 0 1 1 0 DYN PFD down pulse.
0 X X X X X LVL
Ground (dc); for all other cases of 0XXXXX
not specified.
The selections that follow are the same
as for the REF_MON pin.
1 0 0 0 0 0 LVL Ground (dc).
1 0 0 0 0 1 DYN REFA clock.
1 0 0 0 1 0 DYN REFB clock.
1 0 0 0 1 1 DYN Selected reference clock to PLL.
1
0
0
1
0
0
DYN
Unselected reference clock to PLL.
1 0 0 1 0 1 LVL
Both REFA and REFB clocks missing
(active high).
1 0 0 1 1 0 LVL Ground, dc.
1 0 0 1 1 1 LVL REFA present (active high).
1
0
1
0
0
0
LVL
REFB present (active high).
1 0 1 0 0 1 LVL (REFA present) AND (REFB present).