Datasheet

AD9525 Data Sheet
Rev. A | Page 34 of 48
Table 31. REFA, REFB, REFC, B, N, and P Dividers
Reg.
Addr.
(Hex) Bits Bit Name Description
0x011
[7:4]
REFB divider output
high cycles
Divider high cycle word. Normally set to one-half desired divider division minus one:
for example, D/2 – 1; therefore, for Divide = 8, set to 0x03 (8/2 – 1).
Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A
value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).
[3:0]
REFB divider output
low cycles
Divider low cycle word. Normally set to one-half desired divider division minus one:
for example, D/2 – 1; therefore, for Divide = 8, set to 0x03 (8/2 – 1).
Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A
value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).
0x012 [7:4]
REFA divider output
high cycles
Divider high cycle word. Normally set to one-half desired divider division minus one:
for example, D/2 – 1; therefore, for Divide = 8, set to 0x03 (8/2 – 1).
Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A
value of 0x7 means the divider is high for eight input clock cycles (default: 0x0).
[3:0]
REFA divider output
low cycles
Divider low cycle word. Normally set to one-half desired divider division minus one:
for example, D/2 – 1; therefore, for Divide = 8, set to 0x03 (8/2 – 1).
Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A
value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).
0x013 [7:4]
B divider output
high cycles
Divider high cycle word. Normally set to one-half desired divider division minus one:
for example, D/2 – 1; therefore, for Divide = 8, set to 0x03 (8/2 – 1).
Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A
value of 0x7 means the divider is high for eight input clock cycles (default: 0x0).
[3:0]
B divider output
low cycles
Divider low cycle word. Normally set to one-half desired divider division minus one:
for example, D/2 – 1; therefore, for Divide = 8, set to 0x03 (8/2 – 1).
Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A
value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).
0x014 [7:6] Don’t care Don’t care.
5
B divider bypass
Bypasses and powers down the B divider; routes input to divider output.
0: uses divider (default).
1: B divider is set to divide-by-1.
4
REFB divider bypass
Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: REFB divider is set to divide-by-1.
3
REFA divider bypass
Bypasses and powers down the divider; routes input to divider output.
0: use divider (default).
1: REFA divider is set to divide-by-1.
[2:0] P divider prescaler P divider value (B divider prescaler).
Bit 2 Bit 1 Bit 0 Divider Value
0 0 0 1(default)
0 0 1 2
0
1
0
3
0 1 1 4
1 0 0 5
1 0 1 6
1 1 0 Static
1 1 1 Static
0x015 7 Don’t care Don’t care.
6 Reserved 0 (default).
5 Reserved 0 (default).
4 Reserved 0 (default).
3 B divider reset Resets B divider.
0: normal operation (default).
1: holds B divider in reset.