Datasheet

Data Sheet AD9525
Rev. A | Page 33 of 48
REGISTER MAP DESCRIPTIONS
Table 29 through Table 49 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal
address.
Table 29. SPI Mode Serial Port Configuration
Reg.
Addr.
(Hex) Bits Bit Name Description
0x000
7
SDO active
Selects unidirectional or bidirectional data transfer mode.
0: SDIO pin used for write and read; SDO is high impedance (default).
1: SDO used for read; SDIO used for write; unidirectional mode.
6 LSB first/address
increase
SPI MSB or LSB data orientation.
0: data-oriented MSB first; addressing decrements (default).
1: data-oriented LSB first; addressing increments.
5 Soft reset Soft reset.
1 (self-clearing): soft reset; restores default values to internal registers.
4 Unused Unused.
[3:0] Mirror[7:4] Bits[3:0] should always mirror Bits[7:4] so that it does not matter whether the part is in MSB or LSB first mode
(see Register 0x000[6]). Set bits as follows:
Bit 0 = Bit 7
Bit 1 = Bit 6
Bit 2 = Bit 5
Bit 3 = Bit 4
0x004 0 Read back
active registers
Select register bank used for a readback.
0: reads back buffer registers (default).
1: reads back active registers.
Table 30. PFD Charge Pump
Reg.
Addr.
(Hex)
Bits Bit Name Description
0x010 7 PFD polarity Sets the PFD polarity.
0: Positive (higher control voltage produces higher frequency) (default).
1: Negative (higher control voltage produces lower frequency).
[6:4] CP current Charge pump current (with CPRSET = 5.1 kΩ).
Bit 6 Bit 5 Bit 4 I
CP
(mA)
0 0 0 0.6
0 0 1 1.2
0 1 0 1.8
0 1 1 2.4
1 0 0 3.0
1 0 1 3.6
1 1 0 4.2
1 1 1 4.8 (default)
[3:2] CP mode Charge pump operating mode.
Bit 3 Bit 2 Charge Pump Mode
0 0 High impedance state
0 1 Force source current (pump-up)
1 0 Force sink current (pump-down)
1 1 Normal operation (default)
[1:0] Antibacklash
pulse width
See
Table 7 for the maximum operating frequency for each setting.
Bit 1 Bit 0 Antibacklash Pulse Width Mode (ns)
0 0 2.9 (default)
0 1 1.3
1
0
6.0
1 1 2.9