Datasheet

AD9525 Data Sheet
Rev. A | Page 32 of 48
Reg.
Addr.
(Hex)
Register
Name
(MSB)
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
0x0F4 LVPECL OUT4
Don't
care
Don't care Don't care
Power
down
Channel 4,
Channel 5
Don't care
OUT4 PECL output level,
Bits[1:0]
Power down
PECL driver
0x04
0x0F5 LVPECL OUT5
Don't
care
Don't care Don't care Reserved Don't care
OUT5 PECL output level,
Bits[1:0]
Power down
PECL driver
0x04
0x0F6 LVPECL OUT6
Don't
care
Don't care Don't care
Power
down
Channel 6,
Channel 7
Don't care
OUT6 PECL output level,
Bits[1:0]
Power down
PECL driver
0x04
0x0F7 LVPECL OUT7
Don't
care
Don't care Don't care Reserved Don't care
OUT7 PECL output level,
Bits[1:0]
Power down
PECL driver
0x04
0x0F8 Sync output
Don't
care
Don't care Don't care
Power
down sync
channel
Don't care
SYNC_OUT PECL output
level, Bits[1:0]
Power down
PECL driver
0x10
0x0F9
Sync output,
other control
Don't
care
Don't care Don't care
Polarity
CMOS
mode
Enable CMOS drivers,
Bits[1:0]
CMOS mode
Sync out
resampling
edge select
0x00
0x0FA
Drivers
reserved
Don't
care
Don't care Don't care Don't care Don't care
Don't
care
Don't care Don't care 0x00
SYNC Control
0x190
Sync clock
S divider
Sync clock S divider, Bits[7:0] 0x00
0x191
Sync clock
S divider
Sync clock S divider, Bits[15:8] 0x00
0x192
Sync clock
control
Don't
care
Don't care Don't care
Sync
enable
Sync source, Bits[1:0] Sync mode, Bits[1:0] 0x00
VCO, Reference and CLK1 Inputs
0x1E0 VCO divider
Don't
care
Don't care Don't care Don't care Don't care M divider, Bits[2:0] 0x00
Other
0x230 Power-down
Don't
care
Don't care Don't care
Dist all
power-
down
CLKIN power-
down
M
divider
power-
down
Distribution
reference
power-down
PLL power-
down
0x00
0x232 IO_UPDATE
Don't
care
Don't care Don't care Don't care Don't care
Don't
care
Don't care IO_UPDATE 0x00