Datasheet

AD9525 Data Sheet
Rev. A | Page 26 of 48
POWER-DOWN MODES
Chip Power-Down via
PD
The AD9525 can be put into a power-down condition by pulling
the
PD
pin low. Power-down turns off most of the functions and
currents inside the AD9525. The chip remains in this power-down
state until
PD
is brought back to logic high. When taken out of
power-down mode, the AD9525 returns to the settings that
were programmed into its registers prior to the power-down,
unless the registers are changed by new programming while
the
PD
pin is held low.
Powering down the chip shuts down the currents on the chip,
except for the bias current necessary to maintain the LVPECL
outputs in a safe shutdown mode. The LVPECL bias currents are
needed to protect the LVPECL output circuitry from damage that
can be caused by certain termination and load configurations
when tristated. Because this is not a complete power-down, it
can be called sleep mode.
When the AD9525 is in a
PD
power-down, the chip is in the
following state:
• The PLL is off.
• The CLKIN input buffer is off, but the CLKIN input dc
bias circuit is on.
• The reference input buffer is off, but the dc bias circuit is
still on.
• All dividers are off.
• All LVPECL outputs are in safe off mode.
• The serial control port is active, and the chip responds to
commands.
PLL Power-Down
The PLL section of the AD9525 can be selectively powered down.
In this mode, the AD9525 can be used as a 1 to 8 clock buffer by
using the CLKIN as the clock input.
Distribution Power-Down
The distribution section can be powered down by writing
Register 0x230[4] = 1b, which turns off the bias to the distribution
section.
Individual Clock Output Power-Down
Any of the clock distribution outputs can be powered down
into safe power-down mode by individually writing to the
appropriate registers. The register map details the individual
power-down settings for each output. These settings are found
in Register 0x0F0[0] to Register 0x0F7[0].
Individual Clock Channel Power-Down
Any of the clock distribution channels can be powered down
individually by writing to the appropriate registers. Powering
down a clock channel is similar to powering down an individual
driver, but it saves more power because additional circuits are also
powered down. Powering down a clock channel also automatically
powers down the drivers connected to it. The register map details
the individual power-down settings for each output channel.
These settings are found in Register 0x0F0[4], Register 0x0F2[4],
Register 0x0F4[4], and Register 0x0F6[4].