Datasheet

AD9525 Data Sheet
Rev. A | Page 22 of 48
Digital Lock Detect (DLD)
By selecting the proper output through the mux on each pin, the
DLD function is available at the STATUS and REF_MON pins.
The digital lock detect circuit indicates a lock when the time
difference of the rising edges at the PFD inputs is less than a
specified value (the lock threshold). The loss of a lock is indicated
when the time difference exceeds a specified value (the unlock
threshold). Note that the unlock threshold is wider than the
lock threshold, which allows some phase error in excess of the
lock window to occur without chattering on the lock indicator.
The lock detect window timing depends on the value of the
CPRSET resistor, as well as three settings: the digital lock detect
window bit (Register 0x019[1]), the antibacklash pulse width
bits (Register 0x010[1:0], see Table 8), and the lock detect counter
bits (Register 0x019[3:2]). The lock and unlock detection values in
Table 8 are for the nominal value of CPRSET = 5.11 kΩ. Doubling
the CPRSET value to 10 kΩ doubles the values in Table 8.
A lock is not indicated until there is a programmable number
of consecutive PFD cycles with a time difference that is less than
the lock detect threshold. The lock detect circuit continues to
indicate a lock until a time difference greater than the unlock
threshold occurs on a single subsequent cycle. For the lock detect
to work properly, the period of the PFD frequency must be
greater than the unlock threshold. The number of consecutive PFD
cycles required for a lock is programmable (Register 0x018[6:5]).
Note that, in certain low (<500 Hz) loop bandwidth, high phase
margin cases, it is possible that the DLD can chatter during
acquisition. This is normal and occurs because the PFD inputs
are moving slowly in and out of the lock/unlock window during
PLL loop settling. Adjustment of the lock detect counter setting
(Register 0x019[3:2]) can suppress this behavior.
External VCXO/VCO Clock Input (CLKIN/
CLKIN
)
This differential input is used to drive the AD9525 clock
distribution section. The pins are internally self-biased, and the
input signal should be ac-coupled via capacitors.
The CLKIN/
CLKIN
input can be used either as a distribution
only input (with the PLL off) or as a feedback input for an external
VCO/VCXO using the internal PLL. Sample configurations
are illustrated in Figure 19 through Figure 21. Refer to the
manufacturer’s recommendation for VCO terminations; a T or
PI attenuator is often recommended, as illustrated in Figure 19.
For operation using a CMOS input, an external resistive divider
is required to limit the swing on CLKIN (see Table 6 for the
maximum input rating).
Status Monitor
The AD9525 contains three frequency status monitors that are
used to indicate if the PLL reference (or references, in the case
of single-ended mode) and the VCO have fallen below a threshold.
VCO
R
1
C1
AD9525
C2C3
R2
CLKIN
CP
CLKIN
50Ω
V
TUNE
10011-020
ATTENUATOR
1
1
VCO MANUFACTURERS RECOMMEND EITHER A T OR PI ATTENUATOR
TO PREVENT VCO PULLING. REFER TO MANUFACTURER’S
RECOMMENDATION
Figure 19. CLKIN Configured as Single-Ended VCO
CMOS VCXO
R
1
C1
AD9525
C2C3
R2
CLKIN
CP
CLKIN
100kΩ
100kΩ
V
TUNE
10011-021
Figure 20. CLKIN Configured as Single-Ended CMOS VCXO
PECL VCXO
1
1
PROVIDE THE PROPER VCXO
MANUFACTURER PECL TERMINATION.
R
1
C1
AD9525
C2C3
R2
CLKIN
CP
CLKIN
V
TUNE
10011-022
Figure 21. CLKIN Configured as Differential LVPECL VCXO