Datasheet

AD9525 Data Sheet
Rev. A | Page 2 of 48
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Conditions ..................................................................................... 3
Supply Current .............................................................................. 3
Power Dissipation ......................................................................... 3
REFA and REFB Input Characteristics ...................................... 4
REFC Input Characteristics ........................................................ 4
Clock Inputs .................................................................................. 5
PLL Characteristics ...................................................................... 5
PLL Digital Lock Detect .............................................................. 6
Clock Outputs ............................................................................... 6
Timing Characteristics ................................................................ 7
Clock Output Absolute Time Jitter (Clock Generation
Using External 122.88 MHz VCXO).......................................... 8
Clock Output Absolute Time Jitter (Clock Generation
Using External 1475 MHz VCO) ............................................... 8
Clock Output Absolute Time Jitter (Clock Generation
Using External 2.05 GHz VCO) ................................................. 9
Clock Output Absolute Time Jitter (Clock Generation
Using External 3 GHz VCO) ...................................................... 9
Clock Output Additive Phase Noise (Distribution Only;
Clock Input to Distribution Output, Including VCO
Divider) .......................................................................................... 9
PD
,
RESET
, and REF_SEL Pins ................................................ 10
STATUS and REF_MON Pins .................................................. 10
Serial Control Port ..................................................................... 11
Absolute Maximum Ratings ......................................................... 12
Thermal Resistance .................................................................... 12
ESD Caution................................................................................ 12
Pin Configuration and Function Descriptions ........................... 13
Typical Performance Characteristics ........................................... 15
Terminology .................................................................................... 18
Detailed Block Diagram ................................................................ 19
Theory of Operation ...................................................................... 20
Configuration of the PLL .......................................................... 20
Clock Distribution ..................................................................... 23
SYNC_OUT ................................................................................ 23
Reset Modes ................................................................................ 25
Power-Down Modes .................................................................. 26
Serial Control Port ......................................................................... 27
Pin Descriptions ......................................................................... 27
General Operation of Serial Control Port ............................... 27
The Instruction Word (16 Bits) ................................................ 28
MSB/LSB First Transfers ........................................................... 28
Control Registers ............................................................................ 31
Control Register Map Overview .............................................. 31
Register Map Descriptions ............................................................ 33
Applications Information .............................................................. 45
Frequency Planning Using the AD9525 .................................. 45
Using the AD9525 Outputs for ADC Clock Applications .... 45
LVPECL Clock Distribution ..................................................... 46
SYNC_OUT Distribution ......................................................... 46
Outline Dimensions ....................................................................... 47
Ordering Guide ............................................................................... 47
REVISION HISTORY
4/13—Rev. 0 to Rev. A
Changes to One Channel, One Driver and One Channel, Two
Drivers Parameters, Table 3 .............................................................. 4
Change to Figure 18 ........................................................................ 19
Changes to Register 0x01A, Table 28 ............................................ 31
Change to Register 0x000, Bit 6, Table 28 .................................... 33
Changes to Table 35 ........................................................................ 38
Changes to Table 38 ........................................................................ 40
10/12—Revision 0: Initial Version