Datasheet
Data Sheet AD9525
Rev. A | Page 13 of 48
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
VDD3
OUT7
OUT7
4
REF_MON
5
VDD3
6
SYNC_OUT
7
SYNC_OUT
24
RESET
23
PD
22
REFB
21
REFB
20
VDD3
19
GND
18
REFA
17
REFA
16
CP_RSET
15
GND
14
CP
13
VDD_CP
44
OUT3
45
OUT3
46
VDD3
47
OUT2
48
OUT2
43
OUT4
42
OUT4
41
VDD
3
40
OUT5
39
OUT5
38
O
UT6
37
OUT6
TOP
VIEW
(Not to Scale)
AD9525
25
REF_SEL
26
REFC
27
STATUS
28
VDD3
29
CLKIN
30
CLKIN
31
OUT_RSET
32
OUT0
33
OUT0
34
VDD3
35
OUT1
36
OUT1
8
GND
9
SDO
10
SDIO
11
SCLK
12
CS
NOTES
1. THE EXPOSED PAD IS A GROUND CONNECTION ON THE CHIP THAT
MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO
ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE,
AND MECHANICA L STRENGTH BENEFITS.
10011-004
Figure 4. Pin Configuration
Table 22. Pin Function Descriptions
Pin No. Mnemonic Type Description
1
OUT1
O LVPECL Complementary Output 1.
2 OUT1 O LVPECL Output 1.
3 VDD3 P 3.3 V Power Supply for Channel OUT0 and Channel OUT1.
4
OUT0
O LVPECL Complementary Output 0.
5 OUT0 O LVPECL Output 0.
6 OUT_RSET O Clock Distribution Current Set Resistor. Connect a 4.12 kΩ resistor from this pin to GND.
7 CLKIN I
Along with CLKIN
, this pin is the differential input for the clock distribution section.
8
CLKIN
I
Along with CLKIN, this pin is the differential input for the clock distribution section. If a single-ended input is
connected to the CLKIN pin, connect a 0.1 μF bypass capacitor from CLKIN
to ground.
9 VDD3 P 3.3 V Power Supply for CLK Inputs, M Divider, and Output Distribution.
10 STATUS O Lock Detect and Other Status Signals.
11 REFC I Reference Clock Input C. This pin is a CMOS input for the PLL reference.
12 REF_SEL I Reference Input Select. Logic high = REFB. No internal pull-up or pull-down resistor on this pin.
13 VDD_CP P
Power Supply for Charge Pump (CP). VDD3 < VDD_CP < 5.0 V. VDD_CP must still be connected to 3.3 V if the PLL
is not used.
14 CP O
Charge Pump (Output). This pin connects to an external loop filter. This pin can be left unconnected if the
PLL is not used.
15 GND GND Ground for Charge Pump VDD_CP Supply. Connect to ground.
16 CP_RSET O
Charge Pump Current Set Resistor. Connect a 5.1 kΩ resistor from this pin to GND. This resistor can be
omitted if the PLL is not used.
17 REFA I
Reference Clock Input A. Along with REFA
, this pin is the differential input for the PLL reference.
18
REFA
I Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference.
19 GND GND Ground for PLL Power Supply. Connect to ground.
20 VDD3 P 3.3 V Power Supply for PLL.
21 REFB I
Reference Clock Input B. Along with REFB
, this pin is the differential input for the PLL reference.
22
REFB
I Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference.
23
PD
I Chip Power-Down, Active Low. This pin has an internal 30 kΩ pull-up resistor.
24
RESET
I Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor.
25
CS
I Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up resistor.
26 SCLK I Serial Control Port Clock Signal. This pin has an internal 30 kΩ pull-down resistor.
27 SDIO I Serial Control Port Bidirectional Serial Data In/Out.