Datasheet

Data Sheet AD9525
Rev. A | Page 11 of 48
SERIAL CONTROL PORT
Table 19.
Parameter Min Typ Max Unit Test Conditions/Comments
CS (INPUT)
CS has an internal 30 kΩ pull-up resistor
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 2.5 µA
Input Logic 0 Current −112 µA
The minus sign indicates that current is flowing out of the
AD9525, which is due to the internal pull-up resistor
Input Capacitance
2
pF
SCLK (INPUT) SCLK has an internal 30 kΩ pull-down resistor
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 112 µA
Input Logic 0 Current 1 µA
Input Capacitance 2 pF
SDIO (WHEN INPUT)
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 10 nA
Input Logic 0 Current
20
nA
Input Capacitance 2 pF
SDIO, SDO (OUTPUTS) 1 mA load current
Output Logic 1 Voltage 2.7 V
Output Logic 0 Voltage 0.4 V
TIMING
Clock Rate (SCLK, 1/t
SCLK
) 31 MHz
Pulse Width High, t
HIGH
16 ns
Pulse Width Low, t
LOW
16 ns
SDIO to SCLK Setup, t
DS
2 ns
SCLK to SDIO Hold, t
DH
1.1 ns
SCLK to Valid SDIO and SDO, t
DV
12
ns
CS to SCLK Setup and Hold, t
S
, t
H
2 ns
CS Minimum Pulse Width High, t
PWH
3.6 ns