Datasheet

Data Sheet AD9523
Rev. C | Page 53 of 60
Other (Address 0x230 to Address 0x234)
Table 55. Status Signals
Address Bits Bit Name Description
0x230 [7:6] Reserved Reserved
[5:0] Status Monitor 0 control
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Muxout
0 0 0 0 0 0 GND
0
0
0
0
0
1
PLL1 and PLL2 locked
0 0 0 0 1 0 PLL1 locked
0 0 0 0 1 1 PLL2 locked
0
0
0
1
0
0
Both references are missing (REFA and REFB)
0 0 0 1 0 1 Both references are missing and PLL2 is locked
0 0 0 1 1 0 REFB selected (applies only to auto select mode)
0 0 0 1 1 1 REFA is OK
0 0 1 0 0 0 REFB is OK
0 0 1 0 0 1 REF_TEST is OK
0 0 1 0 1 0 VCXO is OK
0 0 1 0 1 1 PLL1 feedback is OK
0 0 1 1 0 0 PLL2 reference clock is OK
0 0 1 1 0 1 Reserved
0 0 1 1 1 0 REFA and REFB are OK
0 0 1 1 1 1 All clocks are OK (except REF_TEST)
0 1 0 0 0 0 PLL1 feedback is divide-by-2
0 1 0 0 0 1 PLL1 PFD down divide-by-2
0 1 0 0 1 0 PLL1 REF divide-by-2
0 1 0 0 1 1 PLL1 PFD up divide-by-2
0 1 0 1 0 0 GND
0 1 0 1 0 1 GND
0 1 0 1 1 0 GND
0 1 0 1 1 1 GND
Note that all bit combinations after 010111
are reserved.