Datasheet

Data Sheet AD9523
Rev. C | Page 51 of 60
Clock Distribution (Register 0x190 to Register 0x1B9)
Table 51. Channel 0 to Channel 13 Control (This Same Map Applies to All 14 Channels)
Address Bits Bit Name Description
0x190 7 Invert divider output Inverts the polarity of the divider’s output clock.
6 Ignore sync 0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5 Power -down channel 1: powers down the entire channel.
0: normal operation.
4 Lower power mode
(differential modes only)
Reduces power used in the differential output modes (LVDS/LVPECL/HSTL). This
reduction may result in power savings, but at the expense of performance. Note that
this bit does not affect output swing and current, just the internal driver power.
1: low strength/lower power.
0: normal operation.
[3:0] Driver mode Driver mode.
Bit 3 Bit 2 Bit 1 Bit 0 Driver Mode
0 0 0 0 Tristate output
0 0 0 1 LVPECL (8 mA)
0 0 1 0 LVDS (3.5 mA)
0 0 1 1 LVDS (7 mA)
0 1 0 0 HSTL-0 (16 mA)
0 1 0 1 HSTL-1 (8 mA)
0 1 1 0 CMOS (both outputs in phase)
+ Pin: true phase relative to divider output
− Pin: true phase relative to divider output
0 1 1 1 CMOS (opposite phases on outputs)
+ Pin: true phase relative to divider output
− Pin: complement phase relative to divider output
1 0 0 0 CMOS
+ Pin: true phase relative to divider output
− Pin: high-Z
1 0 0 1 CMOS
+ Pin: high-Z
− Pin: true phase relative to divider output
1 0 1 0 CMOS
+ Pin: high-Z
− Pin: high-Z
1 0 1 1 CMOS (both outputs in phase)
+ Pin: complement phase relative to divider output
− Pin: complement phase relative to divider output
1 1 0 0 CMOS (both outputs out of phase)
+ Pin: complement phase relative to divider output
− Pin: true phase relative to divider output
1 1 0 1 CMOS
+ Pin: complement phase relative to divider output
− Pin: high-Z
1 1 1 0 CMOS
+ Pin: high-Z
− Pin: complement phase relative to divider output
1 1 1 1 Tristate output
0x191 [7:0] Channel divider,
Bits[7:0] (LSB)
Division = Channel Divider Bits[9:0] + 1. For example, [9:0] = 0 is divided by 1, [9:0] = 1
is divided by 2 … [9:0] = 1023 is divided by 1024. 10-bit channel divider, Bits[7:0] (LSB).
0x192 [7:2] Divider phase Divider initial phase after a sync is asserted relative to the divider input clock (from the
VCO divider output). LSB = ½ of a period of the divider input clock.
Phase = 0: no phase offset.
Phase = 1: ½ period offset, …
Phase = 63: 31 period offset.
[1:0] Channel divider, Bits[9:8] (MSB) 10-bit channel divider, Bits[9:8] (MSB).