Datasheet

AD9522-1
Rev. 0 | Page 8 of 84
TIMING CHARACTERISTICS
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
LVDS OUTPUT RISE/FALL TIMES Termination = 100 Ω across differential pair
Output Rise Time, t
RP
150 350 ps 20% to 80%, measured differentially
Output Fall Time, t
FP
150 350 ps 80% to 20%, measured differentially
PROPAGATION DELAY, t
LVDS
, CLK-TO-LVDS OUTPUT
For All Divide Values 1866 2313 2812 ps High frequency clock distribution configuration
1808 2245 2740 ps Clock distribution configuration
Variation with Temperature 1 ps/°C
OUTPUT SKEW, LVDS OUTPUTS
1
Termination = 100 Ω across differential pair
LVDS Outputs That Share the Same Divider 7 60 ps
LVDS Outputs on Different Dividers 19 162 ps
All LVDS Outputs Across Multiple Parts 432 ps
CMOS OUTPUT RISE/FALL TIMES Termination = open
Output Rise Time, t
RC
625 835 ps 20% to 80%; C
LOAD
= 10 pF
Output Fall Time, t
FC
625 800 ps 80% to 20%; C
LOAD
= 10 pF
PROPAGATION DELAY, t
CMOS
, CLK-TO-CMOS OUTPUT Clock distribution configuration
For All Divide Values 1913 2400 2950 ps
Variation with Temperature 2 ps/°C
OUTPUT SKEW, CMOS OUTPUTS
1
CMOS Outputs That Share the Same Divider 10 55 ps
All CMOS Outputs on Different Dividers 27 230 ps
All CMOS Outputs Across Multiple Parts 500 ps
OUTPUT SKEW, LVDS-TO-CMOS OUTPUT
1
All settings identical; different logic type
Outputs That Share the Same Divider −31 +152 +495 ps LVDS to CMOS on the same part
Outputs That Are on Different Dividers −193 +160 +495 ps LVDS to CMOS on the same part
1
The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
Timing Diagrams
CL
K
t
CMOS
t
CLK
t
LVDS
07220-060
Figure 2. CLK/
CLK
to Clock Output Timing, DIV = 1
DIFFERENTIAL
LVDS
80%
20%
t
RP
t
FP
07220-061
Figure 3. LVDS Timing, Differential
SINGLE-ENDED
CMOS
10pF LOAD
80%
20%
t
RC
t
FC
07220-063
Figure 4. CMOS Timing, Single-Ended, 10 pF Load