Datasheet

AD9522-1
Rev. 0 | Page 76 of 84
Reg.
Addr
(Hex) Bit(s) Name Description
192 [2] Channel 0 power-down Channel 0 powers down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT0/OUT0
, OUT1/OUT1, and OUT2/OUT2 are put into the high
impedance power-down mode by setting this bit.)
192 [0] Disable Divider 0 DCC Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
193 [7:4] Divider 1 low cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
low. A value of 0x3 means the divider is low for four input clock cycles (default: 0x3).
193 [3:0] Divider 1 high cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
high. A value of 0x3 means the divider is high for four input clock cycles (default: 0x3).
194 [7] Divider 1 bypass Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
194 [6] Divider 1 ignore SYNC Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
194 [5] Divider 1 force high Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
194 [4] Divider 1 start high Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
194 [3:0] Divider 1 phase offset Phase offset (default: 0x0).
195 [2] Channel 1 power-down Channel 1 powers down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT3/OUT3
, OUT4/OUT4, and OUT5/OUT5 are put into the high
impedance power-down mode by setting this bit.)
195 [0] Disable Divider 1 DCC Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
196 [7:4] Divider 2 low cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
low. A value of 0x1 means the divider is low for two input clock cycles (default: 0x1).
196 [3:0] Divider 2 high cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
high. A value of 0x1 means the divider is high for two input clock cycles (default: 0x1).
197 [7] Divider 2 bypass Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
197 [6] Divider 2 ignore SYNC Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
197 [5] Divider 2 force high Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
197 [4] Divider 2 start high Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
197 [3:0] Divider 2 phase offset Phase offset (default: 0x0).