Datasheet

AD9522-1
Rev. 0 | Page 74 of 84
Reg.
Addr
(Hex) Bit(s) Name Description
01F [2]
REF2 frequency
> threshold
(read-only)
Readback register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by Register 0x01A[6].
[2] = 0; REF2 frequency is less than the threshold frequency.
[2] = 1; REF2 frequency is greater than the threshold frequency.
01F [1]
REF1 frequency
> threshold
(read-only)
Readback register. Indicates if the frequency of the signal at REF1 is greater than the threshold frequency
set by Register 0x01A[6].
[1] = 0; REF1 frequency is less than the threshold frequency.
[1] = 1; REF1 frequency is greater than the threshold frequency.
01F [0]
Digital lock
detect
(read-only)
Readback register. Digital lock detect.
[0] = 0; PLL is not locked.
[0] = 1; PLL is locked.
Table 53. Output Driver Control
Reg.
Addr
(Hex) Bit(s) Name Description
0F0 [7] OUT0 format Selects the output type for OUT0.
[7] = 0; LVDS (default).
[7] = 1; CMOS.
0F0 [6:5]
OUT0 CMOS
configuration
Sets the CMOS output configuration for OUT0 when 0x0F0[7] = 1.
[6:5] OUT0A OUT0B
00 Tristate Tristate
01 On Tristate
10 Tristate On
11 (default) On On
0F0 [4:3] OUT0 polarity Sets the output polarity for OUT0.
[7] [4] [3] Output Type OUT0A OUT0B
0 (default) X 0 LVDS Noninverting Inverting
0 X 1 LVDS Inverting Noninverting
1 0 (default) 0 (default) CMOS Noninverting Noninverting
1 0 1 CMOS Inverting Inverting
1 1 0 CMOS Noninverting Inverting
1 1 1 CMOS Inverting Noninverting
0F0 [2:1]
OUT0 LVDS
differential
voltage
Sets the LVDS output differential voltage (V
OD
).
[2] [1] I
OD
(mA)
0 0 1.75 (V
OD
= 175 mV for 100 Ω termination across differential pair)
0 (default) 1 (default) 3.5 (V
OD
= 350 mV for 100 Ω termination across differential pair)
1 0 5.25 (V
OD
= 525 mV for 100 Ω termination across differential pair)
1 1 7.0 (V
OD
= 700 mV for 100 Ω termination across differential pair)
0F0 [0]
OUT0 LVDS
power-down
LVDS power-down.
[0] = 0; normal operation (default).
[0] = 1; power-down. Output driver is in a high impedance state.
0F1 [7:0] OUT1 control This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0.
0F2 [7:0] OUT2 control This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0.
0F3 [7:0] OUT3 control This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0.
0F4 [7:0] OUT4 control This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0.
0F5 [7:0] OUT5 control This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0.