Datasheet

AD9522-1
Rev. 0 | Page 68 of 84
Reg.
Addr
(Hex) Bit(s) Name Description
016 [3]
B counter
bypass
B counter bypass. This is only valid when operating the prescaler in FD mode.
[3] = 0; normal (default).
[3] = 1; B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for
the N divider.
016 [2:0] Prescaler P Prescaler: DM = dual modulus and FD = fixed divide. The Prescaler P is part of the feedback divider.
[2] [1] [0] Mode Prescaler
0 0 0 FD Divide-by-1.
0 0 1 FD Divide-by-2.
0 1 0 DM Divide-by-2 and divide-by-3 when A ≠ 0; divide-by-2 when A = 0.
0 1 1 DM Divide-by-4 and divide-by-5 when A ≠ 0; divide-by-4 when A = 0.
1 0 0 DM Divide-by-8 and divide-by-9 when A ≠ 0; divide-by-8 when A = 0.
1 0 1 DM Divide-by-16 and divide-by-17 when A ≠ 0; divide-by-16 when A = 0.
1 1 0 DM Divide-by-32 and divide-by-33 when A ≠ 0; divide-by-32 when A = 0 (default).
1 1 1 FD Divide-by-3.
017 [7:2]
STATUS
pin control
Selects the signal that appears at the STATUS pin. 0x01D[7] must be 0 to reprogram the STATUS pin.
[7] [6] [5] [4] [3] [2]
Level or
Dynamic
Signal Signal at STATUS Pin
0 0 0 0 0 0 LVL Ground, dc (default).
0 0 0 0 0 1 DYN N divider output (after the delay).
0 0 0 0 1 0 DYN R divider output (after the delay).
0 0 0 0 1 1 DYN A divider output.
0 0 0 1 0 0 DYN Prescaler output.
0 0 0 1 0 1 DYN PFD up pulse.
0 0 0 1 1 0 DYN PFD down pulse.
0 X X X X X LVL Ground (dc); for all other cases of 0XXXXX not specified.
The selections that follow are the same as for REFMON.
1 0 0 0 0 0 LVL Ground (dc).
1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode).
1 0 0 0 1 0 DYN REF2 clock (not available in differential mode).
1 0 0 0 1 1 DYN
Selected reference to PLL (differential reference when in
differential mode).
1 0 0 1 0 0 DYN
Unselected reference to PLL (not available in differential
mode).
1 0 0 1 0 1 LVL
Status of selected reference (status of differential reference);
active high.
1 0 0 1 1 0 LVL
Status of unselected reference (not available in differential
mode); active high.
1 0 0 1 1 1 LVL Status of REF1 frequency (active high).
1 0 1 0 0 0 LVL Status of REF2 frequency (active high).
1 0 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency).
1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO).
1 0 1 0 1 1 LVL Status of VCO frequency (active high).
1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2).
1 0 1 1 0 1 LVL DLD; active high.
1 0 1 1 1 0 LVL Holdover active (active high).
1 0 1 1 1 1 LVL LD pin comparator output (active high).
1 1 0 0 0 0 LVL VS (PLL power supply).
1 1 0 0 0 1 DYN
REF1 clock
(differential reference when in differential mode).
1 1 0 0 1 0 DYN
REF2 clock
(not available in differential mode).
1 1 0 0 1 1 DYN
Selected reference to PLL
(differential reference when in
differential mode).