Datasheet

AD9522-1
Rev. 0 | Page 56 of 84
CS
SCLK
SDIO
t
HIGH
t
LOW
t
CLK
t
S
t
DS
t
DH
t
C
BIT N BIT N + 1
0
7220-043
Figure 69. Serial Control Port Timing—Write
Table 45. Serial Control Port Timing
Parameter Description
t
DS
Setup time between data and rising edge of SCLK
t
DH
Hold time between data and rising edge of SCLK
t
CLK
Period of the clock
Setup time between the CS falling edge and SCLK rising edge (start of communication cycle)
t
S
Setup time between SCLK rising edge and the CS
rising edge (end of communication cycle)
t
C
t
HIGH
Minimum period that SCLK should be in a logic high state
t
LOW
Minimum period that SCLK should be in a logic low state
t
DV
SCLK to valid SDIO and SDO (see Figure 67)