Datasheet

AD9522-1
Rev. 0 | Page 50 of 84
SERIAL CONTROL PORT
The AD9522 serial control port is a flexible, synchronous serial
communications port that allows an easy interface with many
industry-standard microcontrollers and microprocessors. The
AD9522 serial control port is compatible with most synchronous
transfer formats, including Philips IC, Motorola® SPI®, and
Intel® SSR protocols. The AD9522 IC implementation deviates
from the classic IC specification on two specifications; these
deviations are documented in Table 14 of this data sheet. The
serial control port allows read/write access to all registers that
configure the AD9522.
SPI/I²C PORT SELECTION
The AD9522 has two serial interfaces, SPI and IC. Users can
select either SPI or IC depending on the states of the three
logic level (high, open, low) input pins, SP1 and SP0. When
both SP1 and SP0 are high, the SPI interface is active. Otherwise,
IC is active with eight different IC slave address (seven bits
wide) settings, see Table 39. The four MSBs of the slave address
are hardware coded as 1011, and the three LSBs are programmed
by SP1 and SP0.
Table 39. Serial Port Mode Selection
SP1 SP0 Address
Low Low I²C, 1011000
Low Open I²C, 1011001
Low High I²C, 1011010
Open Low I²C, 1011011
Open Open I²C, 1011100
Open High I²C, 1011101
High Low I²C, 1011110
High Open I²C, 1011111
High High SPI
I²C SERIAL PORT OPERATION
The AD9522 IC port is based on the IC fast mode standard.
The AD9522 supports both IC protocols: standard mode
(100 kHz) and fast mode (400 kHz).
The AD9522 IC port has a 2-wire interface consisting of a serial
data line (SDA) and a serial clock line (SCL). In an IC bus system,
the AD9522 is connected to the serial bus (data bus SDA and
clock bus SCL) as a slave device, meaning that no clock is generated
by the AD9522. The AD9522 uses direct 16-bit (two bytes)
memory addressing instead of traditional 8-bit (one byte) memory
addressing.
I
2
C Bus Characteristics
Table 40. I
2
C Bus Definitions
Abbreviation Definition
S Start
Sr Repeated start
P
Stop
A
Acknowledge
A
No acknowledge
W
Write
R Read
One pulse on the SCL clock line is generated for each data bit
transferred.
The data on the SDA line must not change during the high
period of the clock. The state of the data line can change only when
the clock on the SCL line is low.
SDA
SCL
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
0
7220-160
Figure 56. Valid Bit Transfer
A start condition is a transition from high to low on the SDA
line while SCL is high. The start condition is always generated
by the master to initialize the data transfer.
A stop condition is a transition from low to high on the SDA
line while SCL is high. The stop condition is always generated
by the master to end the data transfer.
START
CONDITION
S
STOP
CONDITION
P
SD
A
SCL
07220-161
Figure 57. Start and Stop Conditions
A byte on the SDA line is always eight bits long. An acknowledge
bit must follow every byte. Bytes are sent MSB first.
The acknowledge bit is the ninth bit attached to any 8-bit data
byte. An acknowledge bit is always generated by the receiving
device (receiver) to inform the transmitter that the byte has
been received. It is done by pulling the SDA line low during the
ninth clock pulse after each 8-bit data byte.