Datasheet

AD9522-1
Rev. 0 | Page 5 of 84
Parameter Min Typ Max Unit Test Conditions/Comments
Crystal Oscillator
Crystal Resonator Frequency Range 16.62 33.33 MHz
Maximum Crystal Motional Resistance 30 Ω
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency 100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns
45 MHz Antibacklash pulse width = 6.0 ns
Reference Input Clock Doubler Frequency 0.004 50 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns
Antibacklash Pulse Width 1.3 ns 0x017[1:0] = 01b
2.9 ns 0x017[1:0] = 00b; 0x017[1:0] = 11b
6.0 ns 0x017[1:0] = 10b
CHARGE PUMP (CP)
I
CP
Sink/Source Programmable
High Value 4.8 mA
With CPRSET = 5.1 kΩ; higher I
CP
is possible by
changing CPRSET
Low Value 0.6 mA
With CPRSET = 5.1 kΩ; lower I
CP
is possible by
changing CPRSET
Absolute Accuracy 2.5 % Charge pump voltage set to V
CP
/2
CPRSET Range 2.7 10 kΩ
I
CP
High Impedance Mode Leakage 1 nA
Sink-and-Source Current Matching 1 %
0.5 V < V
CP
< VCP − 0.5 V; V
CP
is the voltage on the CP (charge
pump) pin; VCP is the voltage on the VCP power supply pin
I
CP
vs. V
CP
1.5 % 0.5 V < V
CP
< VCP − 0.5 V
I
CP
vs. Temperature 2 % V
CP
= VCP/2 V
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 1 FD 300 MHz
P = 2 FD 600 MHz
P = 3 FD 900 MHz
P = 2 DM (2/3) 600 MHz
P = 4 DM (4/5) 1000 MHz
P = 8 DM (8/9) 2400 MHz
P = 16 DM (16/17) 3000 MHz
P = 32 DM (32/33) 3000 MHz
Prescaler Output Frequency 300 MHz
A, B counter input frequency (prescaler input frequency
divided by P)
PLL N DIVIDER DELAY Register 0x019[2:0]; see Table 52
000 Off
001 385 ps
010 504 ps
011 623 ps
100 743 ps
101 866 ps
110 989 ps
111 1112 ps
PLL R DIVIDER DELAY Register 0x019[5:3]; see Table 52
000 Off
001 365 ps
010 486 ps
011 608 ps
100 730 ps
101 852 ps
110 976 ps
111 1101 ps