Datasheet

AD9522-1
Rev. 0 | Page 47 of 84
1234567
8
910
INPUT TO VCO DIVIDER
INPUT TO CHANNEL DIVIDER
OUTPUT OF
CHANNEL DIVIDER
S
YNC PIN
1
11
12
13 14
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDE
R
OUTPUT CLOCKING
CHANNEL DIVIDE
R
OUTPUT CLOCKING
07220-073
Figure 52. SYNC Timing Pipeline Delay When the VCO Divider Is Used—CLK or VCO Is Input
INPUT TO CLK
INPUT TO CHANNEL DIVIDE
R
OUTPUT OF
CHANNEL DIVIDER
SYNC PIN
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
1234567
8
910
11
12
13 14
1
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDE
R
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
0
7220-074
Figure 53. SYNC Timing Pipeline Delay When the VCO Divider Is Not Used—CLK Input Only
LVDS Output Drivers
The AD9522 output drivers can be configured as either an
LVDS differential output or as a pair of CMOS single-ended
outputs. The LVDS outputs allow for selectable output current
from ~1.75 mA to ~7 mA.
The LVDS output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVDS output can be individually
powered down to save power.
OUT
OUT
3
.5m
A
3
.5m
A
07220-134
Figure 54. LVDS Output Simplified Equivalent Circuit with
3.5 mA Typical Current Source