Datasheet

AD9522-1
Rev. 0 | Page 43 of 84
MODE 0 (INTERNAL VCO MODE)
CLK
CLK
LF
01
DIVIDE BY 1,
2, 3, 4, 5, OR 6
CLOCK
DISTRI-
BUTION
PLL
DISTRIBUTION
CLOCK
MODE 1 (CLOCK DISTRIBUTION MODE)
DISTRIBUTION
CLOCK
MODE 2 (HF CLOCK DISTRIBUTION MODE)
CLK
CLK
LF
01
DIVIDE BY 1,
2, 3, 4, 5, OR 6
CLOCK
DISTRI-
BUTION
PLL
CLK
CLK
LF
01
DIVIDE BY 1,
2, 3, 4, 5, OR 6
CLOCK
DISTRI-
BUTION
PLL
DISTRIBUTION
CLOCK
07220-054
Figure 50. Simplified Diagram of the Three Clock Distribution Operation Modes
CLOCK DISTRIBUTION
A clock channel consists of three LVDS clock outputs or six
CMOS clock outputs that share a common divider. A clock
output consists of the drivers that connect to the output pins.
The clock outputs have either LVDS or CMOS at the pins.
The AD9522 has four clock channels. Each channel has its own
programmable divider that divides the clock frequency applied
to its input. The channel dividers can divide by any integer
from 1 to 32.
The AD9522 features a VCO divider that divides the VCO output
by 1, 2, 3, 4, 5, or 6 before going to the individual channel dividers.
The VCO divider has two purposes. The first is to limit the
maximum input frequency of the channel dividers to 1.6 GHz. The
other is to allow the AD9522 to generate even lower frequencies
than would be possible with only a simple post divider. External
clock signals connected to the CLK input can also use the VCO
divider.
The channel dividers allow for a selection of various duty cycles,
depending on the currently set division. That is, for any specific
division, D, the output of the divider can be set to high for N + 1
input clock cycles and low for M + 1 input clock cycles (where
D = N + M + 2). For example, a divide-by-5 can be high for one
divider input cycle and low for four cycles, or a divide-by-5 can
be high for three divider input cycles and low for two cycles.
Other combinations are also possible.
The channel dividers include a duty-cycle correction function
that can be disabled. In contrast to the selectable duty cycle
just described, this function can correct a non-50% duty cycle
caused by an odd division. However, this requires that the
division be set by M = N + 1.
In addition, the channel dividers allow a coarse phase offset or
delay to be set. Depending on the division selected, the output
can be delayed by up to 15 input clock cycles. For example, if
the frequency at the input of the channel divider is 1 GHz, the
channel divider output can be delayed by up to 15 ns. The
divider outputs can also be set to start high or to start low.
Operation Modes
There are three clock distribution operating modes, see Figure 50.
One of these modes uses the internal VCO, whereas the other
two modes bypass the internal VCO and use the signal provided
on the CLK/
CLK
pins.
In Mode 0 (internal VCO mode), there are two signal paths
available. In the first path, the VCO signal is sent to the VCO
divider and then to the individual channel dividers. In the
second path, the user bypasses the VCO and channel dividers
and sends the VCO signal directly to the drivers.
When CLK is selected as the source, it is not necessary to use the
VCO divider if the CLK frequency is less than the maximum
channel divider input frequency (1600 MHz); otherwise, the
VCO divider must be used to reduce the frequency going to
the channel dividers.
Table 31 shows how the VCO, CLK, and VCO divider are selected.
0x1E1[1:0] selects the channel divider source and determines
whether the VCO divider is used. It is not possible to select the
VCO without using the VCO divider.
Table 31. Operation Modes
0x1E1
Mode [1] [0] Channel Divider Source VCO Divider
2 0 0 CLK Used
1 0 1 CLK Not used
0 1 0 VCO Used
1 1 Not allowed Not allowed