Datasheet

AD9522-1
Rev. 0 | Page 40 of 84
After leaving holdover, the loop then reacquires lock and the
LD pin must go high (if 0x01D[3] = 1) before it can reenter
holdover.
The holdover function always responds to the state of the
currently selected reference (0x01C). If the loop loses lock
during a reference switchover (see the Reference Switchover
section), holdover is triggered briefly until the next reference
clock edge at the PFD.
The following registers affect the automatic/internal holdover
function:
• 0x018[6:5]—lock detect counter. This changes how many
consecutive PFD cycles with edges inside the lock detect
window are required for the DLD indicator to indicate
lock. This impacts the time required before the LD pin can
begin to charge as well as the delay from the end of a
holdover event until the holdover function can be
reengaged.
• 0x018[3]—disable digital lock detect. This bit must be set
to 0 to enable the DLD circuit. Internal/automatic holdover
does not operate correctly without the DLD function enabled.
• 0x01A[5:0]—lock detect pin control. Set this to 000100b to
put it in the current source lock detect mode if using the
LD pin comparator. Load the LD pin with a capacitor of an
appropriate value.
• 0x01D[3]—enable LD pin comparator. 1 = enable; 0 =
disable. When disabled, the holdover function always
senses the LD pin as high.
• 0x01D[1]—external holdover control.
• 0x01D[0]—enable holdover. If holdover is disabled, both
external and automatic/internal holdover are disabled.
In the following example, automatic holdover is configured with
• Automatic reference switchover, prefer REF1.
• Digital lock detect: five PFD cycles, high range window.
• Automatic holdover using the LD pin comparator.
The following registers are set (in addition to the normal PLL
registers):
• 0x018[6:5] = 00b; lock detect counter = five cycles.
• 0x018[4] = 0b; digital lock detect window = high range.
• 0x018[3] = 1b; disable DLD normal operation.
• 0x01A[5:0] = 000100b; program LD pin control to current
source lock detect mode.
• 0x01C[4] = 1b; enable automatic switchover.
• 0x01C[3] = 0b; prefer REF1.
• 0x01C[2:1] = 11b; enable REF1 and REF2 input buffers.
• 0x01D[3] = 1b; enable LD pin comparator.
• 0x01D[1] = 0b; disable external holdover mode and use
automatic/internal holdover mode.
• 0x01D[0] = 1b; enable holdover.
Frequency Status Monitors
The AD9522 contains three frequency status monitors that are
used to indicate if the PLL reference (or references in the case of
single-ended mode) and the VCO have fallen below a threshold
frequency. A diagram showing their location in the PLL is
shown in Figure 48.
The PLL reference monitors have two threshold frequencies:
normal and extended (see Table 17). The reference frequency
monitor thresholds are selected in 0x01F.
PROGRAMMABLE
N DELAY
CLK
CLK
REF1
REF2
BUF
STATUS
STATUS
R
DIVIDER
CLOCK
DOUBLER
VCO STATUS
PROGRAMMABLE
R DELAY
REFERENCE
SWITCHOVER
REF_SEL CPRSET
V
CP
V
S GND RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
BYPASS
LF
LOW DROPOUT
REGULATOR (LDO)
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
PLL
REFERENCE
HOLD
01
DIVIDE BY 1,
2, 3, 4, 5, OR 6
ZERO DELAY BLOCK
FROM CHANNEL
DIVIDER 0
REFIN
OPTIONAL
REFIN
07220-070
Figure 48. Reference and VCO Status Monitors