Datasheet

AD9522-1
Rev. 0 | Page 28 of 84
PROGRAMMABLE
N DELAY
REFIN
CLK
CLK
REF1
REF2
BUF
AMP
AD9522
R
DIVIDER
CLOCK
DOUBLER
STATUS
PROGRAMMABLE
R DELAY
REFERENCE
SWITCHOVER
REF_SEL CPRSET
V
CP
V
S GND RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
BYPASS
LF
LOW DROPOUT
REGULATOR (LDO)
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
PLL
REFERENCE
HOLD
01
DIVIDE BY 1,
2, 3, 4, 5, OR 6
PD
SYNC
REFIN
RESET
EEPROM
DIGITAL
LOGIC
EEPROM
DIVIDE BY
1 TO 32
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
DIVIDE BY
1 TO 32
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
DIVIDE BY
1 TO 32
OUT6
OUT6
OUT7
OUT7
OUT8
OUT8
DIVIDE BY
1 TO 32
OUT9
OUT9
OUT10
OUT10
OUT11
OUT11
ZERO DELAY BLOCK
LVDS/CMOS OUTPUTS
STATUS
STATUS
SP1
SP0
SPI
INTERFACE
I
2
C
INTERFACE
SCLK/SCL
SDIO/SDA
SDO
CS
SERIAL
PORT
DECODE
O
PTIONAL
07220-030
Figure 37. Internal VCO and Clock Distribution (Mode 0)