Datasheet

AD9522-1
Rev. 0 | Page 24 of 84
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100
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10 1k100 100M1M 10M100k10k
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
07220-132
Figure 30. Additive (Residual) Phase Noise,
CLK-to-CMOS @ 250 MHz, Divide-by-4
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100
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1k 100M1M 10M100k10k
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
07220-033
Figure 31. Phase Noise (Absolute) Clock Generation; Internal VCO @
2458 MHz; PFD = 15.36 MHz; LBW = 40 kHz; LVDS Output = 122.88 MHz
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80
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–140
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1k 100M1M 10M100k10k
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
INTEGRATED RMS JITTER (12kHz TO 20MHz): 491fs
INTEGRATED RMS JITTER (20kHz TO 80MHz): 368fs (EXTRAPOLATED)
07220-034
Figure 32. Phase Noise (Absolute) Clock Cleanup; Internal VCO @ 2333 MHz;
PFD = 120 kHz; LBW = 1.92 kHz; LVDS Output = 155.52 MHz
1k 100M1M 10M100k10k
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
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80
–90
–100
–110
–120
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–140
–150
–160
INTEGRATED RMS JITTER (12kHz TO 20MHz): 146fs
07220-135
Figure 33. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112)
@ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVDS Output = 245.76 MHz
C2
62pF
C3
33pF
C1
240nF
C12
220nF
BYPASS
CAPACITOR
FOR LDO
R1
820Ω
R2
390Ω
LFCP
BYPASS
07220-234
Figure 34. PLL Loop Filter Used for Clock Generation Plot (See Figure 31)
C2
1.5nF
C3
2.2nF
C1
4.7µF
C12
220nF
BYPASS
CAPACITOR
FOR LDO
R1
2.1kΩ
R2
3kΩ
LFCP
BYPASS
07220-235
Figure 35. PLL Loop Filter Used for Clock Cleanup Plot (See Figure 32)