Datasheet

AD9522-1
Rev. 0 | Page 19 of 84
Pin No.
Input/
Output
Pin
Type Mnemonic Description
47 O
LVDS or
CMOS
OUT3
(OUT3B) Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
48 O
LVDS or
CMOS
OUT3 (OUT3A)
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
50 O
LVDS or
CMOS
OUT2
(OUT2B) Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
51 O
LVDS or
CMOS
OUT2 (OUT2A)
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
52 O
LVDS or
CMOS
OUT1
(OUT1B) Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
53 O
LVDS or
CMOS
OUT1 (OUT1A)
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
55 O
LVDS or
CMOS
OUT0
(OUT0B) Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
56 O
LVDS or
CMOS
OUT0 (OUT0A)
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
58 O
Current set
resistor
RSET
Clock Distribution Current Set Resistor. Connect a 4.12 kΩ resistor from this pin
to GND.
62 O
Current set
resistor
CPRSET
Charge Pump Current Set Resistor. Connect a 5.1 kΩ resistor from this pin to GND.
This resistor can be omitted if the PLL is not used.
63 I
Reference
input
REFIN
(REF2) Along with REFIN, this is the differential input for the PLL reference. Alternatively,
this pin is a single-ended input for REF2.
64 I
Reference
input
REFIN (REF1)
Along with REFIN
, this is the differential input for the PLL reference. Alternatively,
this pin is a single-ended input for REF1.
EPAD GND GND The exposed die pad must be connected to GND.